How the two processors communicate with eRPC ?

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How the two processors communicate with eRPC ?

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Contributor I

Hello,

I would like to know how the two processors (core0 and core1) can exchange data with erpc in the lpc55s6x. Which peripherical (RAM, UART, etc.) is used? At what rate?

Thanks in advance for your answer.

Best Regards,

Malo

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NXP TechSupport
NXP TechSupport

Malo

In SDK erpc sample I referred,  uses the shared memory for data exchange. The shared memory region is defined and the size can be adjustable in the linker file. The shared memory region start address and the size have to be defined in linker file for each core equally. The shared memory start address is then exported from the linker to the application. Specifically, if you check the linker file of the demo code, both core0 and core1 define a shared memory "rpmsg_sh_mem" at address 0x20031800, length 0x1800. this range of RAM can be accessed by both core0 and core1. then multicore manager component is needed.

 I only know this article including the instruction of shared memory usage. It's simple and readable. 

LPC55xx Multicore Applications with MCUXpresso IDE 

Have a great day,
Jun Zhang

 

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Contributor I

Thank you for the answer.

Have a great day,

Malo

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Contributor I

Yes I already read the example code and I think I know how to use the #erpc and rpmsg thanks to the example codes but the codes are quite high level and my question is more on a lower level (physical level). Is it use a shared RAM memory to exchange data between the two cores? Does this exchange of data is fast?

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NXP TechSupport
NXP TechSupport

Malo

In SDK erpc sample I referred,  uses the shared memory for data exchange. The shared memory region is defined and the size can be adjustable in the linker file. The shared memory region start address and the size have to be defined in linker file for each core equally. The shared memory start address is then exported from the linker to the application. Specifically, if you check the linker file of the demo code, both core0 and core1 define a shared memory "rpmsg_sh_mem" at address 0x20031800, length 0x1800. this range of RAM can be accessed by both core0 and core1. then multicore manager component is needed.

 I only know this article including the instruction of shared memory usage. It's simple and readable. 

LPC55xx Multicore Applications with MCUXpresso IDE 

Have a great day,
Jun Zhang

 

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Contributor I

I already read this AN and I didn't found how the erpc‌ make the two cores exchange data and, especially, at which rate on the LPC55xx/LPC55Sxx.

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NXP TechSupport
NXP TechSupport

Hi Malo

There are 3 eRPC LPCXpresso55s69 SDK\boards\lpcxpresso55s69\multicore_examples

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Hope this can help you.

Have a great day,
Jun Zhang

 

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NXP TechSupport
NXP TechSupport

Hi

I suggest you refer this AN about LPC55xx/LPC55Sxx Dual Core Communication.  

https://www.nxp.com/docs/en/application-note/AN12335.pdf 

Have a great day,
Jun Zhang

 

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