boot stoped at bl2 load image id =3

[LuisSchabarum]

We are using the LS1027AE processor in a custom board with a DDR3 (IS43/46TR16256BL-125K).

But after flash through TAP and reboot the board, we can observe through the serial console that it is stuck after the BL2 loading image id = 3.

The log is below:

VERBOSE: Enable cluster time base
INFO: RCW BOOT SRC is EMMC
VERBOSE: Generic delay timer configured with mult=1 and div=25
INFO: RCW BOOT SRC is EMMC
INFO: esdhc_emmc_init
INFO: Card detected successfully
INFO: esdhc_wait_response: IRQSTAT CTOE set = 10001
INFO: esdhc_wait_response: IRQSTAT CTOE set = 10001
INFO: esdhc_wait_response: IRQSTAT CTOE set = 10001
INFO: init done:
platform clock 400000000
DDR PLL1 1600000000
INFO: Time before programming controller 0 ms
Program controller registers
VERBOSE: total size 1 GB
VERBOSE: Need to wait up to 640 ms
ERROR: Error: Waiting for D_INIT timeout.
ERROR: Writing DDR register(s) failed
ERROR: Programing DDRC error
ERROR: DDR init failed.
NOTICE: Incorrect DRAM0 size is defined in platfor_def.h
VERBOSE: Memory seen by this BL image: 0x1800d000 - 0x1801f000
VERBOSE: Code region: 0x1800d000 - 0x18014000
VERBOSE: Read-only data region: 0x18014000 - 0x18016000
VERBOSE: 1 - DRAM Region 0: 0x20000000 - 0x1bdffffa
ERROR: mmap_add_region_check() failed. error -22
VERBOSE: Secure DRAM Region 0: 0x1bdffffb - 0x1ffffffa
ERROR: mmap_add_region_check() failed. error -22
mmap:
VA:0x1000000 PA:0x1000000 size:0xf000000 attr:0x8 granularity:0x40000000
VA:0x1800d000 PA:0x1800d000 size:0x7000 attr:0x2 granularity:0x40000000
VA:0x18014000 PA:0x18014000 size:0x2000 attr:0x22 granularity:0x40000000
VA:0x1800d000 PA:0x1800d000 size:0x12000 attr:0xa granularity:0x40000000
VA:0x18034000 PA:0x18034000 size:0xc000 attr:0x18 granularity:0x40000000

VERBOSE: Translation tables state:
VERBOSE: Xlat regime: EL3
VERBOSE: Max allowed PA: 0xffffffffff
VERBOSE: Max allowed VA: 0xffffffffff
VERBOSE: Max mapped PA: 0x1803ffff
VERBOSE: Max mapped VA: 0x1803ffff
VERBOSE: Initial lookup level: 0
VERBOSE: Entries @initial lookup level: 2
VERBOSE: Used 3 sub-tables out of 6 (spare: 3)
[LV0] VA:0 size:0x8000000000
[LV1] VA:0 size:0x40000000
[LV2] VA:0 size:0x200000
[LV2] (7 invalid descriptors omitted)
[LV2] VA:0x1000000 PA:0x1000000 size:0x200000 DEV-RW-XN-S
[LV2] VA:0x1200000 PA:0x1200000 size:0x200000 DEV-RW-XN-S
[LV2] VA:0x1400000 PA:0x1400000 size:0x200000 DEV-RW-XN-S
[LV2] VA:0x1600000 PA:0x1600000 size:0x200000 DEV-RW-XN-S
[LV2] VA:0x1800000 PA:0x1800000 size:0x200000 DEV-RW-XN-S
[LV2] VA:0x1a00000 PA:0x1a00000 size:0x200000 DEV-RW-XN-S
[LV2] VA:0x1c00000 PA:0x1c00000 size:0x200000 DEV-RW-XN-S
[LV2] VA:0x1e00000 PA:0x1e00000 size:0x200000 DEV-RW-XN-S
[LV2] VA:0x2000000 PA:0x2000000 size:0x200000 DEV-RW-XN-S
[LV2] VA:0x2200000 PA:0x2200000 size:0x200000 DEV-RW-XN-S
[LV2] VA:0x2400000 PA:0x2400000 size:0x200000 DEV-RW-XN-S
[LV2] VA:0x2600000 PA:0x2600000 size:0x200000 DEV-RW-XN-S
[LV2] VA:0x2800000 PA:0x2800000 size:0x200000 DEV-RW-XN-S
[LV2] VA:0x2a00000 PA:0x2a00000 size:0x200000 DEV-RW-XN-S
[LV2] VA:0x2c00000 PA:0x2c00000 size:0x200000 DEV-RW-XN-S
[LV2] VA:0x2e00000 PA:0x2e00000 size:0x200000 DEV-RW-XN-S
[LV2] VA:0x3000000 PA:0x3000000 size:0x200000 DEV-RW-XN-S
[LV2] VA:0x3200000 PA:0x3200000 size:0x200000 DEV-RW-XN-S
[LV2] VA:0x3400000 PA:0x3400000 size:0x200000 DEV-RW-XN-S
[LV2] VA:0x3600000 PA:0x3600000 size:0x200000 DEV-RW-XN-S
[LV2] VA:0x3800000 PA:0x3800000 size:0x200000 DEV-RW-XN-S
[LV2] VA:0x3a00000 PA:0x3a00000 size:0x200000 DEV-RW-XN-S
[LV2] VA:0x3c00000 PA:0x3c00000 size:0x200000 DEV-RW-XN-S
[LV2] VA:0x3e00000 PA:0x3e00000 size:0x200000 DEV-RW-XN-S
[LV2] VA:0x4000000 PA:0x4000000 size:0x200000 DEV-RW-XN-S
[LV2] VA:0x4200000 PA:0x4200000 size:0x200000 DEV-RW-XN-S
[LV2] VA:0x4400000 PA:0x4400000 size:0x200000 DEV-RW-XN-S
[LV2] VA:0x4600000 PA:0x4600000 size:0x200000 DEV-RW-XN-S
[LV2] VA:0x4800000 PA:0x4800000 size:0x200000 DEV-RW-XN-S
[LV2] VA:0x4a00000 PA:0x4a00000 size:0x200000 DEV-RW-XN-S
[LV2] VA:0x4c00000 PA:0x4c00000 size:0x200000 DEV-RW-XN-S
[LV2] VA:0x4e00000 PA:0x4e00000 size:0x200000 DEV-RW-XN-S
[LV2] VA:0x5000000 PA:0x5000000 size:0x200000 DEV-RW-XN-S
[LV2] VA:0x5200000 PA:0x5200000 size:0x200000 DEV-RW-XN-S
[LV2] VA:0x5400000 PA:0x5400000 size:0x200000 DEV-RW-XN-S
[LV2] VA:0x5600000 PA:0x5600000 size:0x200000 DEV-RW-XN-S
[LV2] VA:0x5800000 PA:0x5800000 size:0x200000 DEV-RW-XN-S
[LV2] VA:0x5a00000 PA:0x5a00000 size:0x200000 DEV-RW-XN-S
[LV2] VA:0x5c00000 PA:0x5c00000 size:0x200000 DEV-RW-XN-S
[LV2] VA:0x5e00000 PA:0x5e00000 size:0x200000 DEV-RW-XN-S
[LV2] VA:0x6000000 PA:0x6000000 size:0x200000 DEV-RW-XN-S
[LV2] VA:0x6200000 PA:0x6200000 size:0x200000 DEV-RW-XN-S
[LV2] VA:0x6400000 PA:0x6400000 size:0x200000 DEV-RW-XN-S
[LV2] VA:0x6600000 PA:0x6600000 size:0x200000 DEV-RW-XN-S
[LV2] VA:0x6800000 PA:0x6800000 size:0x200000 DEV-RW-XN-S
[LV2] VA:0x6a00000 PA:0x6a00000 size:0x200000 DEV-RW-XN-S
[LV2] VA:0x6c00000 PA:0x6c00000 size:0x200000 DEV-RW-XN-S
[LV2] VA:0x6e00000 PA:0x6e00000 size:0x200000 DEV-RW-XN-S
[LV2] VA:0x7000000 PA:0x7000000 size:0x200000 DEV-RW-XN-S
[LV2] VA:0x7200000 PA:0x7200000 size:0x200000 DEV-RW-XN-S
[LV2] VA:0x7400000 PA:0x7400000 size:0x200000 DEV-RW-XN-S
[LV2] VA:0x7600000 PA:0x7600000 size:0x200000 DEV-RW-XN-S
[LV2] VA:0x7800000 PA:0x7800000 size:0x200000 DEV-RW-XN-S
[LV2] VA:0x7a00000 PA:0x7a00000 size:0x200000 DEV-RW-XN-S
[LV2] VA:0x7c00000 PA:0x7c00000 size:0x200000 DEV-RW-XN-S
[LV2] VA:0x7e00000 PA:0x7e00000 size:0x200000 DEV-RW-XN-S
[LV2] VA:0x8000000 PA:0x8000000 size:0x200000 DEV-RW-XN-S
[LV2] VA:0x8200000 PA:0x8200000 size:0x200000 DEV-RW-XN-S
[LV2] VA:0x8400000 PA:0x8400000 size:0x200000 DEV-RW-XN-S
[LV2] VA:0x8600000 PA:0x8600000 size:0x200000 DEV-RW-XN-S
[LV2] VA:0x8800000 PA:0x8800000 size:0x200000 DEV-RW-XN-S
[LV2] VA:0x8a00000 PA:0x8a00000 size:0x200000 DEV-RW-XN-S
[LV2] VA:0x8c00000 PA:0x8c00000 size:0x200000 DEV-RW-XN-S
[LV2] VA:0x8e00000 PA:0x8e00000 size:0x200000 DEV-RW-XN-S
[LV2] VA:0x9000000 PA:0x9000000 size:0x200000 DEV-RW-XN-S
[LV2] VA:0x9200000 PA:0x9200000 size:0x200000 DEV-RW-XN-S
[LV2] VA:0x9400000 PA:0x9400000 size:0x200000 DEV-RW-XN-S
[LV2] VA:0x9600000 PA:0x9600000 size:0x200000 DEV-RW-XN-S
[LV2] VA:0x9800000 PA:0x9800000 size:0x200000 DEV-RW-XN-S
[LV2] VA:0x9a00000 PA:0x9a00000 size:0x200000 DEV-RW-XN-S
[LV2] VA:0x9c00000 PA:0x9c00000 size:0x200000 DEV-RW-XN-S
[LV2] VA:0x9e00000 PA:0x9e00000 size:0x200000 DEV-RW-XN-S
[LV2] VA:0xa000000 PA:0xa000000 size:0x200000 DEV-RW-XN-S
[LV2] VA:0xa200000 PA:0xa200000 size:0x200000 DEV-RW-XN-S
[LV2] VA:0xa400000 PA:0xa400000 size:0x200000 DEV-RW-XN-S
[LV2] VA:0xa600000 PA:0xa600000 size:0x200000 DEV-RW-XN-S
[LV2] VA:0xa800000 PA:0xa800000 size:0x200000 DEV-RW-XN-S
[LV2] VA:0xaa00000 PA:0xaa00000 size:0x200000 DEV-RW-XN-S
[LV2] VA:0xac00000 PA:0xac00000 size:0x200000 DEV-RW-XN-S
[LV2] VA:0xae00000 PA:0xae00000 size:0x200000 DEV-RW-XN-S
[LV2] VA:0xb000000 PA:0xb000000 size:0x200000 DEV-RW-XN-S
[LV2] VA:0xb200000 PA:0xb200000 size:0x200000 DEV-RW-XN-S
[LV2] VA:0xb400000 PA:0xb400000 size:0x200000 DEV-RW-XN-S
[LV2] VA:0xb600000 PA:0xb600000 size:0x200000 DEV-RW-XN-S
[LV2] VA:0xb800000 PA:0xb800000 size:0x200000 DEV-RW-XN-S
[LV2] VA:0xba00000 PA:0xba00000 size:0x200000 DEV-RW-XN-S
[LV2] VA:0xbc00000 PA:0xbc00000 size:0x200000 DEV-RW-XN-S
[LV2] VA:0xbe00000 PA:0xbe00000 size:0x200000 DEV-RW-XN-S
[LV2] VA:0xc000000 PA:0xc000000 size:0x200000 DEV-RW-XN-S
[LV2] VA:0xc200000 PA:0xc200000 size:0x200000 DEV-RW-XN-S
[LV2] VA:0xc400000 PA:0xc400000 size:0x200000 DEV-RW-XN-S
[LV2] VA:0xc600000 PA:0xc600000 size:0x200000 DEV-RW-XN-S
[LV2] VA:0xc800000 PA:0xc800000 size:0x200000 DEV-RW-XN-S
[LV2] VA:0xca00000 PA:0xca00000 size:0x200000 DEV-RW-XN-S
[LV2] VA:0xcc00000 PA:0xcc00000 size:0x200000 DEV-RW-XN-S
[LV2] VA:0xce00000 PA:0xce00000 size:0x200000 DEV-RW-XN-S
[LV2] VA:0xd000000 PA:0xd000000 size:0x200000 DEV-RW-XN-S
[LV2] VA:0xd200000 PA:0xd200000 size:0x200000 DEV-RW-XN-S
[LV2] VA:0xd400000 PA:0xd400000 size:0x200000 DEV-RW-XN-S
[LV2] VA:0xd600000 PA:0xd600000 size:0x200000 DEV-RW-XN-S
[LV2] VA:0xd800000 PA:0xd800000 size:0x200000 DEV-RW-XN-S
[LV2] VA:0xda00000 PA:0xda00000 size:0x200000 DEV-RW-XN-S
[LV2] VA:0xdc00000 PA:0xdc00000 size:0x200000 DEV-RW-XN-S
[LV2] VA:0xde00000 PA:0xde00000 size:0x200000 DEV-RW-XN-S
[LV2] VA:0xe000000 PA:0xe000000 size:0x200000 DEV-RW-XN-S
[LV2] VA:0xe200000 PA:0xe200000 size:0x200000 DEV-RW-XN-S
[LV2] VA:0xe400000 PA:0xe400000 size:0x200000 DEV-RW-XN-S
[LV2] VA:0xe600000 PA:0xe600000 size:0x200000 DEV-RW-XN-S
[LV2] VA:0xe800000 PA:0xe800000 size:0x200000 DEV-RW-XN-S
[LV2] VA:0xea00000 PA:0xea00000 size:0x200000 DEV-RW-XN-S
[LV2] VA:0xec00000 PA:0xec00000 size:0x200000 DEV-RW-XN-S
[LV2] VA:0xee00000 PA:0xee00000 size:0x200000 DEV-RW-XN-S
[LV2] VA:0xf000000 PA:0xf000000 size:0x200000 DEV-RW-XN-S
[LV2] VA:0xf200000 PA:0xf200000 size:0x200000 DEV-RW-XN-S
[LV2] VA:0xf400000 PA:0xf400000 size:0x200000 DEV-RW-XN-S
[LV2] VA:0xf600000 PA:0xf600000 size:0x200000 DEV-RW-XN-S
[LV2] VA:0xf800000 PA:0xf800000 size:0x200000 DEV-RW-XN-S
[LV2] VA:0xfa00000 PA:0xfa00000 size:0x200000 DEV-RW-XN-S
[LV2] VA:0xfc00000 PA:0xfc00000 size:0x200000 DEV-RW-XN-S
[LV2] VA:0xfe00000 PA:0xfe00000 size:0x200000 DEV-RW-XN-S
[LV2] VA:0x10000000 size:0x200000
[LV2] (63 invalid descriptors omitted)
[LV2] VA:0x18000000 size:0x200000
[LV3] VA:0x18000000 size:0x1000
[LV3] (12 invalid descriptors omitted)
[LV3] VA:0x1800d000 PA:0x1800d000 size:0x1000 MEM-RO-EXEC-S
[LV3] VA:0x1800e000 PA:0x1800e000 size:0x1000 MEM-RO-EXEC-S
[LV3] VA:0x1800f000 PA:0x1800f000 size:0x1000 MEM-RO-EXEC-S
[LV3] VA:0x18010000 PA:0x18010000 size:0x1000 MEM-RO-EXEC-S
[LV3] VA:0x18011000 PA:0x18011000 size:0x1000 MEM-RO-EXEC-S
[LV3] VA:0x18012000 PA:0x18012000 size:0x1000 MEM-RO-EXEC-S
[LV3] VA:0x18013000 PA:0x18013000 size:0x1000 MEM-RO-EXEC-S
[LV3] VA:0x18014000 PA:0x18014000 size:0x1000 MEM-RO-XN-S
[LV3] VA:0x18015000 PA:0x18015000 size:0x1000 MEM-RO-XN-S
[LV3] VA:0x18016000 PA:0x18016000 size:0x1000 MEM-RW-XN-S
[LV3] VA:0x18017000 PA:0x18017000 size:0x1000 MEM-RW-XN-S
[LV3] VA:0x18018000 PA:0x18018000 size:0x1000 MEM-RW-XN-S
[LV3] VA:0x18019000 PA:0x18019000 size:0x1000 MEM-RW-XN-S
[LV3] VA:0x1801a000 PA:0x1801a000 size:0x1000 MEM-RW-XN-S
[LV3] VA:0x1801b000 PA:0x1801b000 size:0x1000 MEM-RW-XN-S
[LV3] VA:0x1801c000 PA:0x1801c000 size:0x1000 MEM-RW-XN-S
[LV3] VA:0x1801d000 PA:0x1801d000 size:0x1000 MEM-RW-XN-S
[LV3] VA:0x1801e000 PA:0x1801e000 size:0x1000 MEM-RW-XN-S
[LV3] VA:0x1801f000 size:0x1000
[LV3] (20 invalid descriptors omitted)
[LV3] VA:0x18034000 PA:0x18034000 size:0x1000 DEV-RW-XN-NS
[LV3] VA:0x18035000 PA:0x18035000 size:0x1000 DEV-RW-XN-NS
[LV3] VA:0x18036000 PA:0x18036000 size:0x1000 DEV-RW-XN-NS
[LV3] VA:0x18037000 PA:0x18037000 size:0x1000 DEV-RW-XN-NS
[LV3] VA:0x18038000 PA:0x18038000 size:0x1000 DEV-RW-XN-NS
[LV3] VA:0x18039000 PA:0x18039000 size:0x1000 DEV-RW-XN-NS
[LV3] VA:0x1803a000 PA:0x1803a000 size:0x1000 DEV-RW-XN-NS
[LV3] VA:0x1803b000 PA:0x1803b000 size:0x1000 DEV-RW-XN-NS
[LV3] VA:0x1803c000 PA:0x1803c000 size:0x1000 DEV-RW-XN-NS
[LV3] VA:0x1803d000 PA:0x1803d000 size:0x1000 DEV-RW-XN-NS
[LV3] VA:0x1803e000 PA:0x1803e000 size:0x1000 DEV-RW-XN-NS
[LV3] VA:0x1803f000 PA:0x1803f000 size:0x1000 DEV-RW-XN-NS
[LV3] VA:0x18040000 size:0x1000
[LV3] (447 invalid descriptors omitted)
[LV2] VA:0x18200000 size:0x200000
[LV2] (318 invalid descriptors omitted)
[LV1] VA:0x40000000 size:0x40000000
[LV1] (510 invalid descriptors omitted)
[LV0] VA:0x8000000000 size:0x8000000000
NOTICE: BL2: v1.5(release):1805093e-dirty
NOTICE: BL2: Built : 16:16:58, Jan 8 2021
INFO: Configuring TrustZone Controller
VERBOSE: TrustZone : Configuring region 0 (TZC Interface Base=0x1100000 sec_attr=0x0, ns_devs=0x0)
INFO: Value of region base = 1fdffffb
VERBOSE: TrustZone : Configuring region (TZC Interface Base: 0x1100000, region_no = 1)...
VERBOSE: TrustZone : ... base = 1bdffffb, top = 1fdffffa,
VERBOSE: TrustZone : ... sec_attr = 0x3, ns_devs = 0x0)
INFO: Value of region base = 1ffffffb
VERBOSE: TrustZone : Configuring region (TZC Interface Base: 0x1100000, region_no = 2)...
VERBOSE: TrustZone : ... base = 1fdffffb, top = 1ffffffa,
VERBOSE: TrustZone : ... sec_attr = 0x3, ns_devs = 0xffffffff)
INFO: Value of region base = 3bdffffb
VERBOSE: TrustZone : Configuring region (TZC Interface Base: 0x1100000, region_no = 3)...
VERBOSE: TrustZone : ... base = 20000000, top = 1bdffffa,
VERBOSE: TrustZone : ... sec_attr = 0x3, ns_devs = 0xffffffff)
INFO: BL2: Doing platform setup
INFO: BL2: Loading image id 3
INFO: sd-mmc read done.
VERBOSE: FIP header looks OK.
INFO: sd-mmc read done.
VERBOSE: Using FIP
INFO: sd-mmc read done.
INFO: Loading image id=3 at address 0x3be00000
INFO: sd-mmc read done.

[yipingwang]

According to your log, there is problem at DDR controller initialization. 

Please refer to section "5.2.1.1 TF-A DDR Driver" in LSDKUG_Rev20.12.pdf to modify Plat/nxp/<SOC>/<Board>/platform_def.h and Plat/nxp/<SOC>/<Board>/ddr_init.c according to your target board.

The DDR driver supports the following board level applications for DDR:
• DIMM: Driver reads SPD for configuring DDR timing parameters
• Mock DIMM: Hardcoded timing in place of reading SPD
• Discrete DDR: Driver requires a static DDR configuration to be added

Please choose one DDR initialization method in the above for your target board.

In addition you need to use QCVS tool to calculate the initial DDR initialization parameters according to the DDR data sheet(or reading from SPD), then use DDRv tool to do validation and optimization.

Please refer to DDR Controller Configuration on LS2085/LS2080 Bringing up.

please refer to "QCVS_DDR_User_Guide. pdf" from www.nxp.com.