DDR Controller Configuration on LS2085/LS2080 Bringing up

Document created by Yiping Wang Employee on Nov 23, 2016Last modified by Yiping Wang Employee on Nov 26, 2016
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This document introduces DDR controller configuration to support new type DDR4 SDRAMs during LS2085/LS2080 target board bringing up. These sections are described in the following, DDR controller memory mapped registers related with new SDRAM setting up on LS2085/LS2080 processors; using “DDR Memory Controller Configuration” tool provided in QCVS tool to calculate the basic DDR controller configuration parameters according to the new DIMM datasheet or SPD provided by the manufacture; use DDR validation(DDRv) tool to validate and optimize the DDR configuration by gradually refining an initial DDR configuration up to an optimal configuration; modify CodeWarrior initialization file and u-boot source code with DDR controller optimized configuration parameter.

1. DDR Controller Memory Mapped registers on LS2085/LS2080

2. Generate Basic DDR Controller Configuration Parameters with QCVS Tool

3. Validation and Optimize DDR Controller Configuration with DDRv Tool

4. Porting CodeWarrior initialization file with the custom DDR configuration parameters


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