Power on Sequence for LS2088A

[sekuru_saimukhe]

Hi,

I am using LS2088A in a project.

Below is the power on sequencing which I am implementing in my circuit. 

Initially all the IO and PLL power rails (3.3V, 1.8V, 1.35V, 1V_SVDD, 1V_USBSVDD) are released.

After all these power rails are released then the 1V05 core voltage is released and then the 1V2 DDR supply voltage is released.

Please let me know whether this sequence is fine or any correction is required.

[ufedor]

Described sequence is in accordance with the QorIQ LS2088A/LS2048A Data Sheet, 3.2 Power sequencing assuming that:

1) VDD is at 90% of its value before GnVDD reaches 10% of its value

2) All supply voltages are stable within 400 ms.