I am using LS2088A in my design.
So I want to confirm the power on sequence which I am following.
Initially all the IO powers will be released to the processor and then the CORE 1V05 rail will be released and then the DDR 1V2 will be released to the processor. After all the powers are released then the reset will be released. So kindly let me know whether this power on sequence is fine to proceed or any corrections are required.
Described sequence is in accordance with the QorIQ LS2088A/LS2048A Data Sheet, 3.2 Power sequencing assuming that:
1) VDD is at 90% of its value before GnVDD reaches 10% of its value
2) All supply voltages are stable within 400 ms.