PMIC_POR and PORESET

[trondwang]

Hi NXP,

referring to reset circuit in the schematic of your reference design from Embedded Planet, DES0541_11; page 2:

PMIC_POR_B is connected to R60, but R60 is NOPOP so it will not enter MR_b input of the reset circuit U9.

Instead, PMIC_POR is bypassing the reset circuit through R63 into AND-gate U12 and anded with the RST_ output from U9.

Is there any particular reason why PMIC_POR is bypassing the reset circuit U9?

Could PMIC_POR be connected to MR_b through R60 and instead R63 be NOPOP?

regards Trond Inge 

[alexander_yakov · Accepted solution]

I do not see a significant difference between PMIC_POR_B connected to U9 and to U12. The difference is only in 140ms duration generated by MIC2774N in response to MR input assertion. As per my understanding, connecting to U9 is not necessary in this case, PMIC itself generates proper timing, so direct connection via AND gate U12 is enough.

Have a great day,
Alexander
TIC

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