LS2088A SerDes XFI & 2.5G Query

[KHW]

Hi,

I am trying to understand the SerDes interfaces of LS2088A. For the SerDes 1 and 2 combinations that we are looking for, I am not able to use an SGMII+ (3.125 Gbps or SGMII 2.5) lane. 

My question is: Can we use an XFI interface (10.3125 Gbps) instead to connect to a 2.5G PHY that supports XFI interface? e.g Marvell® Alaska® 88E2010 or BCM84880. Does it need any special attention?

Also, what does 2500BASE-X and 5000BASE-X host interface mean? Is it just SGMII 2.5G and SGMII 5G respectively? I think X is used for gigabit Ethernet transmission over fiber optic, but in this context it is used for MAC-PHY interface in the above part datasheets.

Any help will be much appreciated.

Thanks!

[KHW]

Hi  yipingwang,

Hope you are doing well. Sorry to post in this closed topic, but since it is related to this, I thought to ask the questions here itself. Please let me know if I should create a different topic.

1. We are using LS1046A in one of our products and using XFI interface to 10G AQR113C PHY. Could you please let me know how to check if FLOW CONTROL is enabled on MAC side for LS1046A? Is it the XFI AN Advertisement Register 0? I am not able to understand where to check for it.

2. When you mean special provisioned firmware for AQRate PHY to support speeds lower than 10G, I assume what you mean is different than setting PHY registers for setting up PAUSE capability among other parameters, am I correct?  

3. On AQR113C PHY we have enabled PAUSE operation for full duplex links and Asymmetric PAUSE operation for full
duplex links in the Autonegotiation Advertisement Register: Address 7.10. Do you know if there's anything else to rate adaptation on PHY side that we need to set in the form of registers or is it the special firmware of PHY that is a must?

4. Importantly, if MAC flow control/pause frame is not enabled, what kind of problems can be expected? Will it cause lower throughput or will the link not work altogether or will it cause auto-negotiation or link downgrade issues? 

Any advice would be much appreciated.

Thank you.

[KHW]

Hi yipingwang,

Thank you so much for your time and detailed reply. I appreciate it.

I am trying to understand the same and I will get back with any further queries/comments.

[yipingwang · Accepted solution]

I like the table in the Aquantia (now Marvell) application note.
Our SerDes will operate at a particular baud rate.
10.3125Gbaud for XFI/SFI/USXGMII. 64b/66b encoding. Fixed speed of 10Gbps for XFI/SFI. USXGMII allows rate adaptation for lower speeds.
3.125Gbaud for 2.5G SGMII/2500BASE-X/Over-clocked SGMII. 8b/10b encoding. Fixed speed of 2.5Gbps.
1.25Gbaud for SGMII. 8b/10b encoding. Native speed of 1Gbps. Rate adaptation for 10/100Mbps.

The solution Aquantia PHYs use to support lower speeds if rate adapataion is not available is to send PAUSE frames towards the MAC.
So, if you use XFI to the AQ PHY, the MAC interface is fixed at 10.3125 Gbps and must have flow control enabled to support lower speeds.

We have had an issue with Broadcom in the past because they switch their SerDes internally from 10.3125Gbps to 3.125Gbps to switch for 10G to 2.5G.
This type of switch requires our SoC to choose another RCW and that means a reboot of the chip.
It is a special case to develop a SW workaround for this case to override the RCW without reboot. Validation is needed.

So, it is known that our XFI can work with AQ PHY at 2.5Gbps. PHY vendor provides provisioned firmware for the speeds desired.
I will note they latest offerings, e.g., AQR113 and AQR115, come in different flavors. The AQR113C/AQR115C have a limitation that only TWO physical addreses are available.
So, if you need more than TWO PHYs, you will have a MII mgmt bus conflict for the 3rd AQ PHY. To avoid this, the AQR113/AQR115 versions are better because you have more physical addresses available.

I am not familiar with 5000BASE-X and not sure what freq the SerDes operates at natively. But looks like it is supported by the PHY.
This reference is for a copper PHY. I believe there is an Aquantia SFP module for fiber.

[KHW]

Hi yipingwang,

Sorry for the delay in getting back. As mentioned above/below, I appreciate your detailed explanation.

I have a follow up question/confirmation if you could help please.

We want to have only one 2.5G copper port (RJ45) in our design using LS2048A/2088A and we do NOT have the SGMII+ (3.125 Gbps) SerDes option as we are not able to select it for the required SerDes configurations we want in our design considering other interfaces. 

So, the only option available for us to support this 2.5G port is XFI interface (since other interfaces like XAUI, QSGMII, USXGMII are either not suitable or not supported by either processor or PHY). I assume 10GBASE-KR, which is supported by both, is not a suitable option for implementing a 2.5G port.

What I understand from your explanation is that XFI interface of NXP Layerscape processors (LS2048A/LS2088A) is proven to work with AQrate PHYs at 2.5 Gbps using a special/provisioned firmware provided by Marvell. So, this means there won't be rate adaptation or pause frames needed on MAC side for it to work and we can work with the PHY as if it is in native 2.5G mode. Is this understanding correct? 

However, the provisioned firmware thing is not mentioned in the application note. I would like to understand how it works from usage point of view - whether the PHY part number will be custom ordered based on the provisioned firmware or we would need to do that in our software and program the PHY with the provisioned firmware during board bootup. 

Thanks for your time and help.

[KHW]

Any further help on the above query would be appreciated. 

[yipingwang]

For the AQRate solution, Marvell will provide the firmware for the PHY catered to the customer's needs.
For example, we asked for 10G, 2.5G, 1G, and 100M support for the PHY used on the LX2160A RDB.
So they provided a firmware that uses XFI as the interface towards the MAC. To handle the <10G speeds, the MAC must enable flow control (accept PAUSE frames). I don't think our device will work at 5G if we did not ask for it to be enabled in the PHY.

I can't answer the ordering for PHYs. This is a question for product marketing. Toby Foster or Ghoshank Patel may know the process to order AQRate PHYs from the vendor to meet your requirements.

I know we have steps to flash the firmware for the PHY. I believe the firmware can be loaded from non volatile memory or from the MDIO bus. I believe we chose to do via NVRAM. We have had customers use the MDIO method and wanted a faster MDIO (10Mhz instead of 2.5Mhz).

[KHW]

Thank you so much. Okay, I got it. So, basically we need to ask Marvell for the custom firmware to support any speeds lower than 10G for the XFI interface AND also enable flow control on the MAC to accept pause frames (which I think LS20xxA processors do support).

No worries, I will take care of the ordering part.

Regarding firmware flashing, I see. Going for MDIO bus will naturally be a cheaper alternative, but I get your point. I will check the reference schematics for more understanding.

Thanks again for your kind support. I have accepted your first post as the answer.