LS1088A DDR4 driver porting problem

[jack_huang1]

On LS1088A platform, based on LSDK20.04 version, using onboard particle DDR4 design, the model MT40A512M16LY-075 (64 bit width +8 bit ECC, 4GB in total, 4 pieces of 512M*16 bit DDR4), DDR4 running at 1600MHz, has been produced at present .C file, please see the attachment for details.

The operation process is as follows:

1.  Imported DDR register value, add the values in the generated ddrtfa_1.c file to the ddr_init.c file in the ATF folder as CONFIG_STATIC_DDR in section 5.2.3 of LSDK,
2. Copy all contents of the generated uboot_ddr1.c file to DDR. C file in the u-boot folder,
3. 3. Compile ATF and U-Boot folders in Linux interface, then synthesize image and burn it into NOR flash.

Enable static DDR, Open the # define CONFIG_STATIC_DDR

Refer to the RM file 2.2 System Memory Map and set the starting address to 0x0080_8000_0000.

Use DDR Region #2 as recommended, which is DRAM1 in the code,  Please refer to attachment 1:  

Switch to DRAM1 completely in the BL2 setup file, Please refer to attachment 1:  

In setup of BL31, change addr to 80_80000000 and size to 0x100000000//4GB, Please refer to attachment 1:  

RCW modifies DDR multiplier to 16, modifies DDR_REFCLK_SEL=0, and selects single-ended DDRCLK input clock,Please refer to attachment 1:  

After the compilation is completed, the printed information is Please refer to attachment 1 :

Please check whether the current process is correct and how to modify it. Please help.

Thank you very much!

[TahaBenderli]

Hello,

we are having a DDR4 size problem on LS1088a platform.  We have 4GB DDR4 on the board. When u-boot starts it is confirmed that board has 4GB DDR4. But when we checked on kernel with cat /proc/meminfo or free commands, it shows that RAM is 2GB.  We did tried what @yipingwang post but nothing changed.

Do you have any idea why are we having mismatch DDR size in u-boot and kernel ?

Attached photos you can see the differences.

 

Thanks.

[yipingwang]

If you want to use fixed DDR registers configurations to initialize DDR controller, you need to define CONFIG_STATIC_DDR in platform_def.h, define function board_static_ddr and structure ddr_cfg_regs in plat/nxp/soc-ls1088/ls1088ardb/ddr_init.c in atf folder. You could refer to plat/nxp/soc-ls1046/ls1046ardb/ddr_init.c.

For example

In plat/nxp/soc-ls1088/ls1088ardb/platform_def.h

#define NXP_DDRCLK_FREQ 100000000
#define NUM_OF_DDRC 2
#define DDRC_NUM_DIMM 2
#define CONFIG_STATIC_DDR

In plat/nxp/soc-ls1088/ls1088ardb/ddr_init.c

#ifdef CONFIG_STATIC_DDR
const struct ddr_cfg_regs static_1600 = {
 .cs[0].config = 0x80040322,
.cs[0].bnds = 0x1FF,
.cs[1].config = 0x80000322,
.cs[1].bnds = 0x1FF,
.sdram_cfg[0] = 0xE5004000,
.sdram_cfg[1] = 0x401151,
.sdram_cfg[2] = 0x0,
.timing_cfg[0] = 0x91550018,
.timing_cfg[1] = 0xBAB48E44,
.timing_cfg[2] = 0x490111,
.timing_cfg[3] = 0x10C1000,
.timing_cfg[4] = 0x220002,
.timing_cfg[5] = 0x3401400,
.timing_cfg[6] = 0x0,
.timing_cfg[7] = 0x13300000,
.timing_cfg[8] = 0x1224800,
.timing_cfg[9] = 0x0,
.dq_map[0] = 0x32C57554,
.dq_map[1] = 0xD4BB0BD4,
.dq_map[2] = 0x2EC2F554,
.dq_map[3] = 0xD95D4001,
.sdram_mode[0] = 0x3010211,
.sdram_mode[1] = 0x0,
.sdram_mode[9] = 0x400000,
.sdram_mode[8] = 0x500,
.sdram_mode[2] = 0x10211,
.sdram_mode[3] = 0x0,
.sdram_mode[10] = 0x400,

.sdram_mode[11] = 0x400000,
.sdram_mode[4] = 0x10211,
.sdram_mode[5] = 0x0,
.sdram_mode[12] = 0x400,
.sdram_mode[13] = 0x400000,
.sdram_mode[6] = 0x10211,
.sdram_mode[7] = 0x0,
.sdram_mode[14] = 0x400,
.sdram_mode[15] = 0x400000,
.interval = 0x18600618,
.zq_cntl = 0x8A090705,
.ddr_sr_cntr = 0x0,
.clk_cntl = 0x2000000,
.cdr[0] = 0x80040000,
.cdr[1] = 0xC1,
.wrlvl_cntl[0] = 0x86750607,
.wrlvl_cntl[1] = 0x8090A0B,
.wrlvl_cntl[2] = 0xD0E0F0C,
};

long long board_static_ddr(struct ddr_info *priv)
{

   memcpy(&priv->ddr_reg, &static_1600, sizeof(static_1600)); 
   return 0x100000000; /*hardcoded DDR size 4GB*/
}

[suezure]

Hello, yipingwang

Refer to ddr_init.c in atf\plat\nxp\soc-ls1046\ls1046ardb, I found that:

size = 0x200000000UL; //8GB

simultaneously in atf\plat\nxp\soc-ls1046\ls1046ardb\platform_def.h, I found that:  

#define PLAT_DEF_DRAM0_SIZE 0x80000000 /* 2G */

It seems that PLAT_DEF_DRAM0_SIZE is not required modify when ddr is over 2GB, even though reference manual chapter 2.2 described GPP DRAM Region #1 is 0~2GB at start addr 0x8000_0000

[yipingwang]

Yes, no need to modify PLAT_DEF_DRAM0_SIZE.