/* ** DDR controller #1 initialization code ** Use this code to integrate the DDR controller initialization code into a boot loader code ** ** Copyright : 2019 NXP Semiconductor, Inc. All Rights Reserved. ** SOURCE DISTRIBUTION PERMISSIBLE as directed in End User License Agreement. ** ** http : www.nxp.com ** mail : support@nxp.com */ typedef unsigned int uint32_t; typedef struct ddr_cs { uint32_t bnds; uint32_t config; uint32_t config_2; } ddr_cs_t; typedef struct ddr_cfg_regs { ddr_cs_t cs[4]; uint32_t timing_cfg_0; uint32_t timing_cfg_1; uint32_t timing_cfg_2; uint32_t timing_cfg_3; uint32_t timing_cfg_4; uint32_t timing_cfg_5; uint32_t timing_cfg_7; uint32_t timing_cfg_8; uint32_t sdram_cfg; uint32_t sdram_cfg_2; uint32_t sdram_cfg_3; uint32_t sdram_mode; uint32_t sdram_mode_2; uint32_t sdram_mode_3; uint32_t sdram_mode_4; uint32_t sdram_mode_5; uint32_t sdram_mode_6; uint32_t sdram_mode_7; uint32_t sdram_mode_8; uint32_t sdram_mode_9; uint32_t sdram_mode_10; uint32_t sdram_mode_11; uint32_t sdram_mode_12; uint32_t sdram_mode_13; uint32_t sdram_mode_14; uint32_t sdram_mode_15; uint32_t sdram_mode_16; uint32_t sdram_md_cntl; uint32_t sdram_interval; uint32_t sdram_data_init; uint32_t sdram_clk_cntl; uint32_t init_addr; uint32_t init_ext_addr; uint32_t zq_cntl; uint32_t wrlvl_cntl; uint32_t wrlvl_cntl_2; uint32_t wrlvl_cntl_3; uint32_t sdram_rcw_1; uint32_t sdram_rcw_2; uint32_t sdram_rcw_3; uint32_t sdram_rcw_4; uint32_t sdram_rcw_5; uint32_t sdram_rcw_6; uint32_t sdram_cdr_1; uint32_t sdram_cdr_2; uint32_t err_disable; uint32_t err_int_en; uint32_t err_sbe; } ddr_cfg_regs_t; typedef struct fixed_ddr_param { uint32_t data_rate_low; uint32_t data_rate_high; ddr_cfg_regs_t* p_ddr_cfg; } fixed_ddr_param_t; #define DATARATE_300MHZ 300000000 #define DATARATE_400MHZ 400000000 #define DATARATE_500MHZ 500000000 #define DATARATE_600MHZ 600000000 #define DATARATE_700MHZ 700000000 #define DATARATE_800MHZ 800000000 #define DATARATE_900MHZ 900000000 #define DATARATE_1000MHZ 1000000000 #define DATARATE_1200MHZ 1200000000 #define DATARATE_1300MHZ 1300000000 #define DATARATE_1400MHZ 1400000000 #define DATARATE_1500MHZ 1500000000 #define DATARATE_1600MHZ 1600000000 #define DATARATE_1700MHZ 1700000000 #define DATARATE_1800MHZ 1800000000 #define DATARATE_1900MHZ 1900000000 #define DATARATE_2000MHZ 2000000000 #define DATARATE_2100MHZ 2100000000 #define DATARATE_2200MHZ 2200000000 #define DATARATE_2300MHZ 2300000000 #define DATARATE_2400MHZ 2400000000 /* swaps the bits [i.e. changes endianess] of a 32-bit value */ #define SWAP(x) ( \ (((x) >> 24) & 0xFF) \ | (((x) << 8) & 0xFF0000) \ | (((x) >> 8) & 0xFF00) \ | (((x) << 24) & 0xFF000000) \ ) #define VALUE_OF(x) \ SWAP(x) #define DDRmc1_CS0_BNDS VALUE_OF(0xFF) #define DDRmc1_CS1_BNDS VALUE_OF(0x00) #define DDRmc1_CS0_CONFIG VALUE_OF(0x80010412) #define DDRmc1_CS1_CONFIG VALUE_OF(0x00) #define DDRmc1_CS0_CONFIG_2 VALUE_OF(0x00) #define DDRmc1_CS1_CONFIG_2 VALUE_OF(0x00) #define DDRmc1_CS2_BNDS VALUE_OF(0x00) #define DDRmc1_CS3_BNDS VALUE_OF(0x00) #define DDRmc1_CS2_CONFIG VALUE_OF(0x00) #define DDRmc1_CS3_CONFIG VALUE_OF(0x00) #define DDRmc1_CS2_CONFIG_2 VALUE_OF(0x00) #define DDRmc1_CS3_CONFIG_2 VALUE_OF(0x00) #define DDRmc1_TIMING_CFG_3 VALUE_OF(0x01111000) #define DDRmc1_TIMING_CFG_0 VALUE_OF(0xFF55000C) #define DDRmc1_TIMING_CFG_1 VALUE_OF(0xBEB40E44) #define DDRmc1_TIMING_CFG_2 VALUE_OF(0x0049111C) #define DDRmc1_SDRAM_CFG VALUE_OF(0x65200000) #define DDRmc1_SDRAM_CFG2 VALUE_OF(0x00401070) #define DDRmc1_MODE_1 VALUE_OF(0x01010211) #define DDRmc1_MODE_2 VALUE_OF(0x00) #define DDRmc1_MODE_3 VALUE_OF(0x00) #define DDRmc1_MODE_4 VALUE_OF(0x00) #define DDRmc1_MODE_5 VALUE_OF(0x00) #define DDRmc1_MODE_6 VALUE_OF(0x00) #define DDRmc1_MODE_7 VALUE_OF(0x00) #define DDRmc1_MODE_8 VALUE_OF(0x00) #define DDRmc1_MODE_CONTROL VALUE_OF(0x00) #define DDRmc1_INTERVAL VALUE_OF(0x18600618) #define DDRmc1_MEM_INIT_VALUE VALUE_OF(0xDEADBEEF) #define DDRmc1_CLK_CTRL VALUE_OF(0x02800000) #define DDRmc1_WRLVL_CNTL VALUE_OF(0x86750606) #define DDRmc1_WRLVL_CNTL_2 VALUE_OF(0x07060608) #define DDRmc1_WRLVL_CNTL_3 VALUE_OF(0x09080908) #define DDRmc1_INIT_ADDR VALUE_OF(0x00) #define DDRmc1_INIT_EXT_ADDR VALUE_OF(0x00) #define DDRmc1_TIMING_CFG_4 VALUE_OF(0x0022D501) #define DDRmc1_TIMING_CFG_5 VALUE_OF(0x04401400) #define DDRmc1_ZQ_CNTL VALUE_OF(0x8A090705) #define DDRmc1_RCW_1 VALUE_OF(0x00) #define DDRmc1_RCW_2 VALUE_OF(0x00) #define DDRmc1_CDR_1 VALUE_OF(0x80040000) #define DDRmc1_CDR_2 VALUE_OF(0x81) #define DDRmc1_SDRAM_CFG_3 VALUE_OF(0x00) #define DDRmc1_TIMING_CFG_7 VALUE_OF(0x23340000) #define DDRmc1_TIMING_CFG_8 VALUE_OF(0x02336800) #define DDRmc1_DQ_MAP0 VALUE_OF(0x00) #define DDRmc1_DQ_MAP1 VALUE_OF(0x00) #define DDRmc1_DQ_MAP2 VALUE_OF(0x00) #define DDRmc1_DQ_MAP3 VALUE_OF(0x00) #define DDRmc1_RCW_3 VALUE_OF(0x00) #define DDRmc1_RCW_4 VALUE_OF(0x00) #define DDRmc1_RCW_5 VALUE_OF(0x00) #define DDRmc1_RCW_6 VALUE_OF(0x00) #define DDRmc1_MODE_9 VALUE_OF(0x0701) #define DDRmc1_MODE_10 VALUE_OF(0x04800000) #define DDRmc1_MODE_11 VALUE_OF(0x00) #define DDRmc1_MODE_12 VALUE_OF(0x00) #define DDRmc1_MODE_13 VALUE_OF(0x00) #define DDRmc1_MODE_14 VALUE_OF(0x00) #define DDRmc1_MODE_15 VALUE_OF(0x00) #define DDRmc1_MODE_16 VALUE_OF(0x00) #define DDRmc1_ERR_DISABLE VALUE_OF(0x00) #define DDRmc1_ERR_INT_EN VALUE_OF(0x00) #define DDRmc1_ERR_SBE VALUE_OF(0x00010000) #define CLK_ADJ_MASK 0x07C00000 #define CLK_ADJ_OFFSET 22 #define WRLVL_START_MASK 0x0000001F #define HSE_MASK 0x00000008 #define HSE_OFFSET 3 #define CLK_ADJ ((0x02800000 & CLK_ADJ_MASK) >> CLK_ADJ_OFFSET) #define WRLVL_START (0x86750606 & WRLVL_START_MASK) #define HALF_STRENGTH_ENABLE ((0x65200000 & HSE_MASK) >> HSE_OFFSET) ddr_cfg_regs_t ddr_cfg_regs_1 = { .cs[0].bnds = DDRmc1_CS0_BNDS, .cs[1].bnds = DDRmc1_CS1_BNDS, .cs[0].config = DDRmc1_CS0_CONFIG, .cs[1].config = DDRmc1_CS1_CONFIG, .cs[0].config_2 = DDRmc1_CS0_CONFIG_2, .cs[1].config_2 = DDRmc1_CS1_CONFIG_2, .cs[2].bnds = DDRmc1_CS2_BNDS, .cs[3].bnds = DDRmc1_CS3_BNDS, .cs[2].config = DDRmc1_CS2_CONFIG, .cs[3].config = DDRmc1_CS3_CONFIG, .cs[2].config_2 = DDRmc1_CS2_CONFIG_2, .cs[3].config_2 = DDRmc1_CS3_CONFIG_2, .timing_cfg_0 = DDRmc1_TIMING_CFG_0, .timing_cfg_1 = DDRmc1_TIMING_CFG_1, .timing_cfg_2 = DDRmc1_TIMING_CFG_2, .timing_cfg_3 = DDRmc1_TIMING_CFG_3, .timing_cfg_4 = DDRmc1_TIMING_CFG_4, .timing_cfg_5 = DDRmc1_TIMING_CFG_5, .timing_cfg_7 = DDRmc1_TIMING_CFG_7, .timing_cfg_8 = DDRmc1_TIMING_CFG_8, .sdram_cfg = DDRmc1_SDRAM_CFG, .sdram_cfg_2 = DDRmc1_SDRAM_CFG2, .sdram_cfg_3 = DDRmc1_SDRAM_CFG_3, .sdram_mode = DDRmc1_MODE_1, .sdram_mode_2 = DDRmc1_MODE_2, .sdram_mode_3 = DDRmc1_MODE_3, .sdram_mode_4 = DDRmc1_MODE_4, .sdram_mode_5 = DDRmc1_MODE_5, .sdram_mode_6 = DDRmc1_MODE_6, .sdram_mode_7 = DDRmc1_MODE_7, .sdram_mode_8 = DDRmc1_MODE_8, .sdram_mode_9 = DDRmc1_MODE_9, .sdram_mode_10 = DDRmc1_MODE_10, .sdram_mode_11 = DDRmc1_MODE_11, .sdram_mode_12 = DDRmc1_MODE_12, .sdram_mode_13 = DDRmc1_MODE_13, .sdram_mode_14 = DDRmc1_MODE_14, .sdram_mode_15 = DDRmc1_MODE_15, .sdram_mode_16 = DDRmc1_MODE_16, .sdram_md_cntl = DDRmc1_MODE_CONTROL, .sdram_interval = DDRmc1_INTERVAL, .sdram_data_init = DDRmc1_MEM_INIT_VALUE, .sdram_clk_cntl = DDRmc1_CLK_CTRL, .init_addr = DDRmc1_INIT_ADDR, .init_ext_addr = DDRmc1_INIT_EXT_ADDR, .zq_cntl = DDRmc1_ZQ_CNTL, .wrlvl_cntl = DDRmc1_WRLVL_CNTL, .wrlvl_cntl_2 = DDRmc1_WRLVL_CNTL_2, .wrlvl_cntl_3 = DDRmc1_WRLVL_CNTL_3, .sdram_rcw_1 = DDRmc1_RCW_1, .sdram_rcw_2 = DDRmc1_RCW_2, .sdram_rcw_3 = DDRmc1_RCW_3, .sdram_rcw_4 = DDRmc1_RCW_4, .sdram_rcw_5 = DDRmc1_RCW_5, .sdram_rcw_6 = DDRmc1_RCW_6, .sdram_cdr_1 = DDRmc1_CDR_1, .sdram_cdr_2 = DDRmc1_CDR_2, .err_disable = DDRmc1_ERR_DISABLE, .err_int_en = DDRmc1_ERR_INT_EN, .err_sbe = DDRmc1_ERR_SBE };