LS1046 CW TAP:DDR validation Error

[Hmc510]

LS1046 DDR 8G . 1800MT

I modified the code in project ATF with ddrTfa_1.c 

DDR validation:

[mrudangshelat-13 · Accepted solution]

Hi @Hmc510,

There are few possible reasons for the error as mentioned below:

1. The training sequence that the controller follows to calibrate the read data path was not able to complete. This would probably only happen if there was a hard failure on the memory interface caused by board-level issues or incorrect controller settings.
   

2. Incorrect termination of MDICx signals.

3. Write leveling calibration was not able to complete. This relates to improper settings of the DDR_WRLVL_CNTL register or board-level issues.

Regards,

Mrudang