LS1043ARGW SD TFA boot problem

[hakjunoh]

I have LS1043ARGW custom boards and LS1043ARDB-PD boards. I am trying to boot from an sd card.

And I need OP-TEE, so I have to boot with TFA. However, there is a problem that the boot does not work. So I built it as tfa, not SECURE_tfa. Of course the ASK binary works fine.

1. u-boot (Needed for building atf)

I made u-boot patch file with reference to RGW u-boot. And patched to u-boot LSDK-20.04.

Then I set to ls1043argw_tfa_config and built.

2. atf

atf LSDK-20.04 was built using the following options:

PLAT=ls1043ardb

BOOT_MODE=sd

RCW=(ls1043ardb-sdboot-rcw.bin) <- attached file

BL33=u-boot.bin

FIPTOOL=tools/fiptool/fiptool

CREATE_PBL=/plat/nxp/tools/create_pbl

BYTE_SWAP=/plat/nxp/tools/byte_swap

DEBUG=1

3. write to sd card

bl2_sd.pbl and fip.bin generated by building atf were written to the sd card.

Write to SD
dd if=/dev/zero of=/dev/mmcblk0 bs=1M count=10 dd if=bl2_sd.pbl of=/dev/mmcblk0 bs=512 seek=8 dd if=fip.bin of=/dev/mmcblk0 bs=512 seek=2048

4. boot

When booting this sd card from RDB

RDB boot log

INFO: RCW BOOT SRC is SD/EMMC INFO: RCW BOOT SRC is SD/EMMC INFO: Card detected successfully INFO: init done: INFO: time base 30 ms NOTICE: Fixed DDR on board INFO: Time after parsing SPD 4 ms INFO: Time before programming controller 8 ms NOTICE: 2 GB DDR4, 32-bit, CL=11, ECC off INFO: Time used by DDR driver 18 ms NOTICE: BL2: v1.5(debug):LSDK-20.04 NOTICE: BL2: Built : 07:46:25, May 7 2020 INFO: CALL: bl2_arch_setup INFO: CALL: bl2_plat_preload_setup INFO: Configuring TZASC-380 INFO: CALL: bl2_load_images INFO: BL2: Doing platform setup INFO: BL2: Loading image id 3 INFO: sd-mmc read done. INFO: sd-mmc read done. U-Boot 2019.10 (May 07 2020 - 07:46:23 +0100) SoC: LS1043AE Rev1.1 (0x87920011) Clock Configuration: CPU0(A53):1600 MHz CPU1(A53):1600 MHz CPU2(A53):1600 MHz CPU3(A53):1600 MHz Bus: 300 MHz DDR: 1600 MT/s FMAN: 600 MHz Reset Configuration Word (RCW): 00000000: 06100010 0c000000 00000000 00000000 00000010: 14550002 80004002 60106000 c1002000 00000020: 00000000 00000000 00000000 01030940 00000030: 00000000 00003004 00000096 00000001 Model: LS1043A RGW Board Board: LS1043ARGW, boot from SD Invalid setting SERDES Reference Clocks: SD1_CLK1 = 156.25MHZ, SD1_CLK2 = 100.00MHZ DRAM: 1.9 GiB (DDR4, 32-bit, CL=11, ECC off) Using SERDES1 Protocol: 5205 (0x1455) SEC0: RNG instantiated Flash: 128 MiB NAND: 512 MiB MMC: FSL_SDHC: 0 Loading Environment from MMC... *** Warning - bad CRC, using default environment EEPROM: NXID v1 In: serial Out: serial Err: serial Net: MMC read: dev # 0, block # 18432, count 128 ... Fman1: Data at 00000000f7a38f60 is not a firmware PCIe0: pcie@3400000 disabled PCIe1: pcie@3500000 Root Complex: no link PCIe2: pcie@3600000 Root Complex: no link No ethernet found. Hit any key to stop autoboot: 0

but when booting from RGW

RGW boot log

?NFO: RCW BOOT SRC is SD/EMMC INFO: RCW BOOT SRC is SD/EMMC INFO: Card detected successfully INFO: init done: INFO: time base 30 ms NOTICE: Fixed DDR on board INFO: Time after parsing SPD 5 ms INFO: Time before programming controller 8 ms NOTICE: 2 GB DDR4, 32-bit, CL=11, ECC off INFO: Time used by DDR driver 18 ms NOTICE: BL2: v1.5(debug):LSDK-20.04 NOTICE: BL2: Built : 08:27:14, Apr 22 2020 INFO: Configuring TZASC-380 INFO: BL2: Doing platform setup INFO: BL2: Loading image id 3 INFO: sd-mmc read done. WARNING: Firmware Image Package header check failed. WARNING: Failed to obtain reference to image id=3 (-2) ERROR: BL2: Failed to load image (-2) Authentication failure

I have looked at the operation problems of eSDHC, but confirmed that it works in 1bit little-endian mode on the source.
As a result of several boot checks, the ATF confirmed that the FIP header value was read from 0x10_0000.
In the case of RDB, the FIP header read the value of 0x10_0000 correctly, but it was confirmed that RGW reads the value of 0x10_0008.

I have not yet figured out what is causing this issue.

Please help me.

best regards.

[yipingwang · Accepted solution]

Hello hakjun oh,

In the TF-A boot flow, DDR initialization is not required in U-Boot. DDR initialization is a part of TF-A.

DDR init code can be added to <atf_dir>/plat/nxp/soc-<soc-name>/<soc-name>ardb/ddr_init.c.

You need to modify ddr_raw_timing in atf/plat/nxp/soc-ls1043/ls1043ardb/ddr_init.c according to your custom board.

Thanks,

Yiping

[hakjunoh]

Hi Yiping.

So, is the RAM timing problem the reason why BL2 Image is read from 0x10_0008 when LS1043ARGW is booted?

Thanks,

hakjun oh

[yipingwang]

Hello hakjun oh,

Yes, DDR initialization problem is the cause.

Thanks,

Yiping

[hakjunoh]

Yiping.

Unfortunately, the ram timing value has been changed, but the same message is output.

The source uses the MT40A512M8HX-093E, but our custom board uses the MT40A512M8RH-083E.

The changes are as follows.

plat/nxp/soc-ls1043/ls1043ardb/ddr_init.c

diff --git a/plat/nxp/soc-ls1043/ls1043ardb/ddr_init.c b/plat/nxp/soc-ls1043/ls1043ardb/ddr_init.c index 705adb014..776204d57 100644 --- a/plat/nxp/soc-ls1043/ls1043ardb/ddr_init.c +++ b/plat/nxp/soc-ls1043/ls1043ardb/ddr_init.c @@ -92,33 +92,33 @@ int ddr_board_options(struct ddr_info *priv)       return 0; } -/* DDR model number: MT40A512M8HX-093E */ +/* DDR model number: MT40A512M8RH-083E */ struct dimm_params ddr_raw_timing = {       .n_ranks = 1,       .rank_density = 2147483648u,       .capacity = 2147483648u,       .primary_sdram_width = 32, -     .n_row_addr = 15, -     .n_col_addr = 10, +    .n_row_addr = 15, //row addressing +    .n_col_addr = 10, //col addressing       .bank_group_bits = 2,       .burst_lengths_bitmask = 0x0c, -     .tckmin_x_ps = 938, -     .tckmax_ps = 1500, +    .tckmin_x_ps = 834, //tck min +    .tckmax_ps = 938, //tck max       .caslat_x = 0x000DFA00, -     .taa_ps = 13500, -     .trcd_ps = 13500, -     .trp_ps = 13500, -     .tras_ps = 33000, -     .trc_ps = 46500, -     .twr_ps = 15000, -     .trfc1_ps = 260000, -     .trfc2_ps = 160000, -     .trfc4_ps = 110000, -     .tfaw_ps = 21000, -     .trrds_ps = 3700, -     .trrdl_ps = 5300, -     .tccdl_ps = 5355, -     .refresh_rate_ps = 7800000, +    .taa_ps = 13320, //taa +    .trcd_ps = 13320, //trcd +    .trp_ps = 13320, //trp +    .tras_ps = 32000, //tras +    .trc_ps = 45320, //tras + trp +    .twr_ps = 15000, //twr +    .trfc1_ps = 260000, //trfc1 +    .trfc2_ps = 160000, //trfc2 +    .trfc4_ps = 110000, //trfc4 +    .tfaw_ps = 21000, //tfaw +    .trrds_ps = 3300, //trrds +    .trrdl_ps = 4900, //trrdl +    .tccdl_ps = 5000, //tccdl +    .refresh_rate_ps = 7800000, //refi       .rc = 0x1f, };

Did I miss something or change it wrong?

[yipingwang]

Hello hakjun oh,

You could use QCVS DDRv tool to validate and optimize DDR controller initialization parameters.

Would you please try your new generated ATF image on LS1043ARDB to check whether you encounter similar problem as booting from RGW?

Thanks,

Yiping

[hakjunoh]

Hi Yiping.

Are you trying to boot an ATF image for RGW into RDB?
This is the RDB log in the table above, but DDR_DEBUG option enabled, it looks like this:

RDB log with DDR_DEBUG

픭?NFO: RCW BOOT SRC is SD/EMMC INFO: RCW BOOT SRC is SD/EMMC INFO: esdhc_emmc_init INFO: Card detected successfully INFO: init done: INFO: platform clock 300000000 INFO: DDR PLL1 1600000000 INFO: DDR PLL2 0 INFO: time base 37 ms INFO: Parse DIMM SPD(s) INFO: cal cs INFO: cs_in_use = 1 INFO: cs_on_dimm[0] = 1 NOTICE: Fixed DDR on board INFO: Time after parsing SPD 13 ms INFO: Synthesize configurations INFO: cs 0 INFO: odt_rd_cfg 0x0 INFO: odt_wr_cfg 0x4 INFO: odt_rtt_norm 0x3 INFO: odt_rtt_wr 0x0 INFO: auto_precharge 0 INFO: cs 1 INFO: odt_rd_cfg 0x0 INFO: odt_wr_cfg 0x0 INFO: odt_rtt_norm 0x0 INFO: odt_rtt_wr 0x0 INFO: auto_precharge 0 INFO: cs 2 INFO: odt_rd_cfg 0x0 INFO: odt_wr_cfg 0x0 INFO: odt_rtt_norm 0x0 INFO: odt_rtt_wr 0x0 INFO: auto_precharge 0 INFO: cs 3 INFO: odt_rd_cfg 0x0 INFO: odt_wr_cfg 0x0 INFO: odt_rtt_norm 0x0 INFO: odt_rtt_wr 0x0 INFO: auto_precharge 0 INFO: ctlr_init_ecc 0 INFO: x4_en 0 INFO: ap_en 0 INFO: ctlr_intlv 0 INFO: ctlr_intlv_mode 0 INFO: ba_intlv 0x0 INFO: data_bus_used 1 INFO: otf_burst_chop_en 0 INFO: burst_length 0x8 INFO: dbw_cap_shift 0 INFO: Assign binding addresses INFO: ctlr_intlv 0 INFO: rank density 0x80000000 INFO: CS 0 INFO: base_addr 0x0 INFO: size 0x80000000 INFO: base 0x0 INFO: Total mem by assignment is 0x80000000 INFO: Calculate controller registers INFO: Skip CL mask for this speed 0x400 INFO: Skip caslat 0x400 INFO: cs_in_use = 0x1 INFO: cs0 INFO: _config = 0x80040322 INFO: cs[0].bnds = 0x7f INFO: sdram_cfg[0] = 0xc50c0000 INFO: sdram_cfg[1] = 0x401100 INFO: sdram_cfg[2] = 0x0 INFO: timing_cfg[0] = 0x91550018 INFO: timing_cfg[1] = 0xbab48c42 INFO: timing_cfg[2] = 0x48c111 INFO: timing_cfg[3] = 0x10c1000 INFO: timing_cfg[4] = 0x2 INFO: timing_cfg[5] = 0x3401400 INFO: timing_cfg[6] = 0x0 INFO: timing_cfg[7] = 0x13300000 INFO: timing_cfg[8] = 0x2114600 INFO: timing_cfg[9] = 0x0 INFO: dq_map[0] = 0x0 INFO: dq_map[1] = 0x0 INFO: dq_map[2] = 0x0 INFO: dq_map[3] = 0x0 INFO: sdram_mode[0] = 0x3010210 INFO: sdram_mode[1] = 0x0 INFO: sdram_mode[9] = 0x4000000 INFO: sdram_mode[8] = 0x500 INFO: sdram_mode[2] = 0x10210 INFO: sdram_mode[3] = 0x0 INFO: sdram_mode[10] = 0x400 INFO: sdram_mode[11] = 0x4000000 INFO: sdram_mode[4] = 0x10210 INFO: sdram_mode[5] = 0x0 INFO: sdram_mode[12] = 0x400 INFO: sdram_mode[13] = 0x4000000 INFO: sdram_mode[6] = 0x10210 INFO: sdram_mode[7] = 0x0 INFO: sdram_mode[14] = 0x400 INFO: sdram_mode[15] = 0x4000000 INFO: interval = 0x18600618 INFO: zq_cntl = 0x8a090705 INFO: ddr_sr_cntr = 0x0 INFO: clk_cntl = 0x3000000 INFO: cdr[0] = 0x80040000 INFO: cdr[1] = 0xa181 INFO: wrlvl_cntl[0] = 0x8675f607 INFO: wrlvl_cntl[1] = 0x7090807 INFO: wrlvl_cntl[2] = 0x7070707 INFO: debug[28] = 0x46 INFO: Time before programming controller 267 ms INFO: Program controller registers INFO: Reading debug[9] as 0x1f001d00 INFO: Reading debug[10] as 0x22002000 INFO: cpo_min 0x1d INFO: cpo_max 0x22 INFO: debug[28] 0x700046 INFO: Optimal cpo_sample 0x46 INFO: *0x1080000 = 0x7f INFO: *0x1080080 = 0x80040322 INFO: *0x1080100 = 0x10c1000 INFO: *0x1080104 = 0x91550018 INFO: *0x1080108 = 0xbab48c42 INFO: *0x108010c = 0x48c111 INFO: *0x1080110 = 0xc50c0000 INFO: *0x1080114 = 0x401100 INFO: *0x1080118 = 0x3010210 INFO: *0x1080120 = 0x600041f INFO: *0x1080124 = 0x18600618 INFO: *0x1080128 = 0xdeadbeef INFO: *0x1080130 = 0x3000000 INFO: *0x1080160 = 0x2 INFO: *0x1080164 = 0x3401400 INFO: *0x108016c = 0x13300000 INFO: *0x1080170 = 0x8a090705 INFO: *0x1080174 = 0xc675f607 INFO: *0x1080190 = 0x7090807 INFO: *0x1080194 = 0x7070707 INFO: *0x1080200 = 0x10210 INFO: *0x1080208 = 0x10210 INFO: *0x1080210 = 0x10210 INFO: *0x1080220 = 0x500 INFO: *0x1080224 = 0x4000000 INFO: *0x1080228 = 0x400 INFO: *0x108022c = 0x4000000 INFO: *0x1080230 = 0x400 INFO: *0x1080234 = 0x4000000 INFO: *0x1080238 = 0x400 INFO: *0x108023c = 0x4000000 INFO: *0x1080250 = 0x2114600 INFO: *0x1080280 = 0xeeeeee06 INFO: *0x1080284 = 0x11111111 INFO: *0x1080288 = 0xffffff10 INFO: *0x108028c = 0xff INFO: *0x1080290 = 0xffff0001 INFO: *0x1080b20 = 0x8080 INFO: *0x1080b24 = 0x80000000 INFO: *0x1080b28 = 0x80040000 INFO: *0x1080b2c = 0xa181 INFO: *0x1080bf8 = 0x20501 INFO: *0x1080bfc = 0x200 INFO: *0x1080f04 = 0x2 INFO: *0x1080f08 = 0xb INFO: *0x1080f0c = 0x14000c20 INFO: *0x1080f24 = 0x1f001d00 INFO: *0x1080f28 = 0x22002000 INFO: *0x1080f34 = 0x5000 INFO: *0x1080f48 = 0x1 INFO: *0x1080f4c = 0x94000000 INFO: *0x1080f50 = 0xf000e00 INFO: *0x1080f54 = 0x12001100 INFO: *0x1080f58 = 0xe000e00 INFO: *0x1080f5c = 0xe000e00 INFO: *0x1080f60 = 0xe000000 INFO: *0x1080f70 = 0x700046 INFO: *0x1080f9c = 0x13001300 INFO: *0x1080fa0 = 0x13001300 INFO: *0x1080fb0 = 0x3 INFO: *0x1080fb4 = 0xf0f0e10 INFO: *0x1080fb8 = 0xf0f0e0e INFO: *0x1080fbc = 0xf0f0e10 INFO: *0x1080fc0 = 0xf0f0f0f INFO: *0x1080fc4 = 0xf0f0f11 INFO: *0x1080fc8 = 0xf100f0f INFO: *0x1080fcc = 0xf0e0e10 INFO: *0x1080fd0 = 0xf100f0f INFO: *0x1080fd4 = 0xf0f0f0f INFO: *0x1080fd8 = 0xf0f0f0f INFO: *0x1080fdc = 0xf0f0f0f INFO: *0x1080fe0 = 0xf0f0f0f INFO: *0x1080fe4 = 0xf0f0f0f INFO: *0x1080fe8 = 0xf0f0f0f INFO: *0x1080fec = 0xf0f0f0f INFO: *0x1080ff0 = 0xf0f0f0f INFO: *0x1080ff4 = 0xf0f0f0f INFO: *0x1080ff8 = 0xf0f0f0f NOTICE: 2 GB DDR4, 32-bit, CL=11, ECC off INFO: Time used by DDR driver 516 ms NOTICE: BL2: v1.5(debug):LSDK-20.04 NOTICE: BL2: Built : 01:45:57, May 29 2020 INFO: Configuring TZASC-380 INFO: BL2: Doing platform setup INFO: BL2: Loading image id 3 INFO: sd-mmc read done. INFO: sd-mmc read done. INFO: sd-mmc read done. INFO: Loading image id=3 at address 0xfbe00000 INFO: sd-mmc read done. INFO: Image id=3 loaded: 0xfbe00000 - 0xfbe0d644 INFO: BL2: Loading image id 5 INFO: sd-mmc read done. INFO: sd-mmc read done. INFO: sd-mmc read done. INFO: sd-mmc read done. INFO: sd-mmc read done. INFO: Loading image id=5 at address 0x82000000 INFO: sd-mmc read done. INFO: Image id=5 loaded: 0x82000000 - 0x820b886f NOTICE: BL2: Booting BL31 INFO: Entry point address = 0xfbe00000 INFO: SPSR = 0x3cd NOTICE: BL31: v1.5(debug):LSDK-20.04 NOTICE: BL31: Built : 01:45:52, May 29 2020 NOTICE: Welcome to LS1043 BL31 Phase INFO: ARM GICv2 driver initialized INFO: BL31: Initializing runtime services WARNING: BL31: cortex_a53: CPU workaround for 835769 was missing! WARNING: BL31: cortex_a53: CPU workaround for 843419 was missing! INFO: BL31: cortex_a53: CPU workaround for 855873 was applied INFO: BL31: Preparing for EL3 exit to normal world INFO: Entry point address = 0x82000000 INFO: SPSR = 0x3c9 U-Boot 2019.10 (May 29 2020 - 02:11:12 +0100) SoC: LS1043AE Rev1.1 (0x87920011) Clock Configuration: CPU0(A53):1600 MHz CPU1(A53):1600 MHz CPU2(A53):1600 MHz CPU3(A53):1600 MHz Bus: 300 MHz DDR: 1600 MT/s FMAN: 600 MHz Reset Configuration Word (RCW): 00000000: 06100010 0c000000 00000000 00000000 00000010: 14550002 80004002 60106000 c1002000 00000020: 00000000 00000000 00000000 01030940 00000030: 00000000 00003004 00000096 00000001 Model: LS1043A RGW Board Board: LS1043ARGW, boot from SD Invalid setting SERDES Reference Clocks: SD1_CLK1 = 156.25MHZ, SD1_CLK2 = 100.00MHZ DRAM: 1.9 GiB (DDR4, 32-bit, CL=11, ECC off) Using SERDES1 Protocol: 5205 (0x1455) SEC0: RNG instantiated Flash: 128 MiB NAND: 512 MiB MMC: FSL_SDHC: 0 Loading Environment from MMC... *** Warning - bad CRC, using default environment EEPROM: NXID v1 In: serial Out: serial Err: serial Net: MMC read: dev # 0, block # 18432, count 128 ... Fman1: Data at 00000000f7a38f60 is not a firmware PCIe0: pcie@3400000 disabled PCIe1: pcie@3500000 Root Complex: no link PCIe2: pcie@3600000 Root Complex: no link No ethernet found. Hit any key to stop autoboot: 0

Thanks,

hakjun oh

[yipingwang]

Hello hakjun oh,

Please apply your DDR patch for LS1043ARGW  on packages/firmware/atf/plat/nxp/soc-ls1043/ls1043ardb/ddr_init.c in ATF source code, then move build/firmware/atf/ and build/firmware/u-boot/, rebuild ATF image for LS1043ARDB and verify it on LS1043ARDB.

Thanks,

Yiping

[hakjunoh]

Hi Yiping.

Is there anything else I can do?

Thanks,

hakjun oh

[yipingwang]

Hello hakjun oh,

Please check whether RCW for LS1043ARGW is correct. 

Do you have CodeWarrior and CodeWarrior TAP? If yes, please create a bareboard project in CodeWarrior and check whether the sample project can run on the target board. In CodeWarrior initialization file, please modify DDR initialization parameters with your debug data, please use USE_SAFE_RCW = True in CW initialization file to use the hard-coded RCW.

Thanks,

Yiping

[hakjunoh]

Hi Yiping.

Yes. The bare board project worked fine.

I think there perhaps have problem with RCW so I modified ASK's RCW to work with SDHC and booted, but the result is the same.

What shall we do next?

Reset Configuration Word (RCW):
00000000: 08100010 0a000000 00000000 00000000
00000010: 14550002 80004002 60106000 c1002000
00000020: 00000000 00000000 00000000 01030940
00000030: 00000000 00003004 00000096 00000001

Thanks,

hakjun oh

[yipingwang]

Hello hakjun oh,

In CodeWarrior initialization file, please configure USE_SAFE_RCW = False, please configure the target board as booting from SD card, then try whether the bareboard project can work fine.

Thanks,

Yiping

[hakjunoh]

Hi Yiping.

Oops, sorry. I didn't understand the prev answer to the question well.

In the previous question, RGW booting with the USE_SAFE_RCW = True option causes the machine to hang.

RGW booted with SAFE_RCW
INFO: RCW BOOT SRC is SD/EMMC INFO: RCW BOOT SRC is SD/EMMC INFO: esdhc_emmc_init INFO: Card detected successfully INFO: init done: INFO: platform clock 400000000 INFO: DDR PLL1 1600000000 INFO: DDR PLL2 0 INFO: time base 32 ms INFO: Parse DIMM SPD(s) INFO: cal cs INFO: cs_in_use = 1 INFO: cs_on_dimm[0] = 1 NOTICE: Fixed DDR on board INFO: Time after p

And when the diagnosis starts, an error is displayed in 2 items.

Test Name	Info
...	...
Run target initialization script	DDR: initialization failed (ERR_DETECT = 0x00000080).
Test DDR memory access	Memory verification failed. First mismatch was found at address 0x80000000. Expected 'aa', but found '55'.
...	...

But likewise, booting the RDB with the USE_SAFE_RCW = True option cause hang.

RDB booted with SAFE_RCW

INFO: RCW BOOT SRC is SD/EMMC
INFO: RCW BOOT SRC is SD/EMMC
INFO: esdhc_emmc_init
INFO: Card detected successfully
INFO: init done:
INFO: platform clock 400000000
INFO: DDR PLL1 1600000000
INFO: DDR PLL2 0
INFO: time base 32 ms
INFO: Parse DIMM SPD(s)
INFO: cal cs
INFO: cs_in_use = 1
INFO: cs_on_dimm[0] = 1
NOTI

However, the diagnosis has not error.

Thanks,

hakjun oh

[yipingwang]

Please use DDRv to connect your custom board to optimize and validate your DDR configuration parameters on the custom board.

[hakjunoh]

Hi Yiping.

I found something while I was looking at the board. I thought it was MT40A512M88HX-093E because it was written as MT40A512M8HX-093E in the RDB source and schematic. However, I confirmed that the FBGA codes of RDB and RGW are the same.

Different results were obtained when the Validation Test was performed by matching the set values using Codewarrior DDRv. In RDB, all tests are Passed, but in RGW, all tests are Failed.

RGW DDR	RDB DDR

The more I do, the more I can't figure out the cause. What more should I do?

I will continue to validate DDR configuration parameters.

Thanks,

hakjun oh

[hakjunoh]

Yiping.

I found reason of failed DDR validation in Codewarrior DDRv. It should have set DQ values. I didn't know if there was this option.
Either way, the results are good. Now I should check if there is any DQ setting in the ATF source.

RGW DDR Validation

Thanks,

hakjun oh

[hakjunoh]

Hi Yiping.

The problem has been resolved.

plat/nxp/soc-ls1043/ls1043ardb/ddr_init.c

diff --git a/plat/nxp/soc-ls1043/ls1043ardb/ddr_init.c b/plat/nxp/soc-ls1043/ls1043ardb/ddr_init.c index 705adb014..776204d57 100644 --- a/plat/nxp/soc-ls1043/ls1043ardb/ddr_init.c +++ b/plat/nxp/soc-ls1043/ls1043ardb/ddr_init.c @@ -92,33 +92,33 @@ int ddr_board_options(struct ddr_info *priv)       return 0; } /* DDR model number: MT40A512M8HX-093E */ struct dimm_params ddr_raw_timing = {       .n_ranks = 1,       .rank_density = 2147483648u,       .capacity = 2147483648u,       .primary_sdram_width = 32,       .n_row_addr = 15,       .n_col_addr = 10,       .bank_group_bits = 2,       .burst_lengths_bitmask = 0x0c,       .tckmin_x_ps = 938,       .tckmax_ps = 1500,       .caslat_x = 0x000DFA00,       .taa_ps = 13500,       .trcd_ps = 13500,       .trp_ps = 13500,       .tras_ps = 33000,       .trc_ps = 46500,       .twr_ps = 15000,       .trfc1_ps = 260000,       .trfc2_ps = 160000,       .trfc4_ps = 110000,       .tfaw_ps = 21000,       .trrds_ps = 3700,       .trrdl_ps = 5300,       .tccdl_ps = 5355,       .refresh_rate_ps = 7800000, +    .dq_mapping[0] = 0x15, +    .dq_mapping[1] = 0x36, +    .dq_mapping[2] = 0x15, +    .dq_mapping[3] = 0x35, +    .dq_mapping[4] = 0x15, +    .dq_mapping[5] = 0x36, +    .dq_mapping[6] = 0x16, +    .dq_mapping[7] = 0x36, +    .dq_mapping[8] = 0x1, +    .dq_mapping[9] = 0x21, +    .dq_mapping[10] = 0x0, +    .dq_mapping[11] = 0x0, +    .dq_mapping[12] = 0x0, +    .dq_mapping[13] = 0x0, +    .dq_mapping[14] = 0x0, +    .dq_mapping[15] = 0x0, +    .dq_mapping[16] = 0x0, +    .dq_mapping[17] = 0x0, +    .dq_mapping_ors = 0,       .rc = 0x1f, };

Thank you very much.

hakjun oh

[ChienNQ]

Dear Hakjunoh, 

I have same problem. Can you share me how to mapping data? 

Thanks so much!

[hakjunoh]

Hi Yiping.

I'm not sure what I understand, but DDR patch for LS1043ARGW applied to flexbuilder. And rebuilded u-boot and atf.

The rebuilt image was written to SD and booted from LS1043ARDB.

The boot log is:

Boot log on LS1043ARDB with DDR patch applied.

NOTICE: Fixed DDR on board NOTICE: 2 GB DDR4, 32-bit, CL=11, ECC off NOTICE: BL2: v1.5(release):LSDK-20.04 NOTICE: BL2: Built : 15:22:06, Jun 1 2020 NOTICE: BL31: v1.5(release):LSDK-20.04 NOTICE: BL31: Built : 15:22:10, Jun 1 2020 NOTICE: Welcome to LS1043 BL31 Phase U-Boot 2019.10-dirty (Jun 01 2020 - 15:12:34 +0900) SoC: LS1043AE Rev1.1 (0x87920011) Clock Configuration: CPU0(A53):1600 MHz CPU1(A53):1600 MHz CPU2(A53):1600 MHz CPU3(A53):1600 MHz Bus: 300 MHz DDR: 1600 MT/s FMAN: 600 MHz Reset Configuration Word (RCW): 00000000: 06100010 0c000000 00000000 00000000 00000010: 14550002 80004002 60106000 c1002000 00000020: 00000000 00000000 00000000 01030940 00000030: 00000000 00003004 00000096 00000001 Model: LS1043A RDB Board Board: LS1043ARGW, boot from SD Invalid setting SERDES Reference Clocks: SD1_CLK1 = 156.25MHZ, SD1_CLK2 = 100.00MHZ DRAM: 1.9 GiB (DDR4, 32-bit, CL=11, ECC off) Using SERDES1 Protocol: 5205 (0x1455) SEC0: RNG instantiated FSL_SDHC: 0 MMC read: dev # 0, block # 18944, count 128 ... Not a microcode Flash: 128 MiB NAND: 512 MiB MMC: Loading Environment from MMC... *** Warning - bad CRC, using default environment EEPROM: NXID v1 In: serial Out: serial Err: serial Net: MMC read: dev # 0, block # 18432, count 128 ... Fman1: Data at 00000000f7a380b0 is not a firmware PCIe0: pcie@3400000 disabled PCIe1: pcie@3500000 Root Complex: no link PCIe2: pcie@3600000 Root Complex: no link No ethernet found. Hit any key to stop autoboot: 10

Thanks,

hakjun oh