LS1043A DCFG_CCSR_RSTRQSR1 register does not change

[jack_huang1]

Dear；

        We set WDOG3 active and timeout value 3s, It works and system was reset after 3S;See Figure 1.

        But we found that there's no change in DCFG_CCSR_RSTRQSR1 register.See Figure 2.

        According the the LS1043ARM, the reset reason should be record in the bit 0, but it did not.

        What are the conditions that trigger a change in the DCFG_CCSR_RSTRQSR1 register at reset? How do I read the value of the DCFG_CCSR_RSTRQSR1 register to be a valid value?

          Thank you!

[yipingwang]

To which reset signal(PORESET_B or HRESET_B), the RESET_REQ_B pin is connected?
DCFG_CCSR_RSTRQSR1 register stores the status bits to record how reset occured last time the LS1043A device is working.
If RESET_REQ_B pin is connected to HRESET_B, then no change in value will be seen at bit 0(CORE_WDOG3_RST_RR).
If connected to POREST_B, bit 0 will be set to 1.
You can also refer/check section 13.3.14 Reset Request Status Register (DCFG_CCSR_RSTRQSR1) in LS1043ARM for its description and usage.

[jack_huang1]

Dear Yingping;

          It connected to POREST_B, bit 0  still is 0.  What are the conditions for wdog3 to fire? Thank you!

[yipingwang]

Please refer to the following update from the AE team.

If customer has any provision to connect RESET_REQ_B signal to HRESET_B, do that and observe the bit 0. Do let us know if any change occurs.

[yipingwang]

Apologies for my last response. Some confusion occurs on understanding the issue. If customer has any provision to connect RESET_REQ_B signal to HRESET_B, do that and observe the bit 0. Do let us know if any change occurs.

RESET_REQ_B is an internal block request that asserts HRESET_B or PORESET_B. In your case, it is asserting PORESET_B, which resets the register to its default or initial state. To see the source of the output reset assertion in DCFG_CCSR_RSTRQSR1 , RESET_REQ_B  should be connected to HRESET_B.

[jack_huang1]

Dear Yiping；

          Motherboard measured RESET_REQ connected to HRSET, can not achieve reset? And then it goes down and it stays down. Please check the attached schematic to see what the reason is.

          Thank you!

           FYI!

[yipingwang]

1) R5587 is marked as "DNI", I am not sure if output from 4th pin of buffer IC U5021 is connected to HRESET_N.
2) Similarly, R5049 is marked as "DNI", I am not sure if RESET_REQ_N signal is connected to HRESET_N through this resistor.
3) We can also see at a point where R5446 is connected, RESET_REQ_N is also directly connected to POR_B through R5586 which is wrong because it does not meet the timing requirement of POR_B.
4) PORESET_B and HRESET_B have a minimum assertion time of 1ms and 32 SYSCLKs respectively which can be fulfilled if RESET_REQ_B is provided as an input to the reset block IC U5001.
RESET_REQ_B causes assertion of either PORESET_B or HRESET_B. If PORESET_B is asserted, it initializes all registers to its default state and most I/O drivers are released to high impedance means RESET_REQ_B will behave as an input now. You can refer section 4.4.1 Power-on reset sequence of LS1043ARM for detail information.
At this time, PORESET_B assertion causes RESET_REQ_B to go down but due to its high impedance state, it again pulled up within a short period of time which inhibits PORESET_B to meet its minimum assertion time.
Therefore, the RESET_REQ_B signal should be provided as an input to external reset IC which converts any short pulse detected to a bigger one through some internal logic and PORESET_B and HRESET_B timing requirement can be fulfilled.

[jack_huang1]

Dear Yiping；

          HRESET_B and PORESET_B are currently described in the NXP LS1043ARM manual as follows:

          PORESET_B ：Power on reset. Causes the chip to abort all current internal and external
transactions and set all registers to their default values. PORESET_B may be
asserted completely asynchronously with respect to all other signals.

         HRESET_B：Hard reset. Causes the chip to abort all current internal and external transactions
and set all registers to their default values. HRESET_B may be asserted completely
asynchronously with respect to all other signals. HRESET_B is driven as an output
during the first part of the power on reset sequence, after which, it becomes an
input, allowing external devices to stall/hold the reset sequence. See Hard reset
sequence for more information.

         2 reset will be auses the chip to abort all current internal and external
transactions and set all registers to their default values. What is the difference between HRESET_B and PORESET_B? Is default values  “0”? Does HRESET_B restore the DCFG_CCSR_RSTRQSR1 register to 0?

          Thank you!

[yipingwang]

Will back to you.

[jack_huang1]

Dear yiping;

            Did you get any results on this question? Thank you!

[yipingwang]

Confirming with the AE team now.

[yipingwang]

During HRESET_B, SoC follows exactly the same procedure as PORESET_B. But additional sampling of POR configuration pins occurs at the rising edge of PORESET_B signal (when PORESET_B is de-asserted) to determine the RCW source.
When SoC is out of reset, default value of PORESET_B & HRESET_B is high.
On setting WDOG3 active with timeout value of 3s, system reset after 3s => mw.w 0x2a70000 0534
WDOG3_WRSR register should indicate that the reset was due to watchdog timeout via the TOUT bit. Bit 14 should be 1 => md.w 0x2a70004 would show 0012
Further, register DCFG_CCSR_RSTRQSR1 should show 1 for bit 0, the CORE_WDOG3_RST_RR field, to indicate that WDOG reset request from WDOG3 is active.
The bit 0 of DCFG_CCSR_RSTRQSR1 register will restore its value to 1 if RESET_REQ_B is connected to HRESET_B. If RESET_REQ_B is connected to PORESET_B, then bit 0 of DCFG_CCSR_RSTRQSR1 register will restore its value to 0.