DDR can't work when I disable DDRC data_init at BL2 stage

[Simon666]

I'm optimizing BL2 boot time based on lx2160 yocto kirkstone version, get a issue when disable ddr data init.

I check the spec of LX2160ARM.pdf and see D_INIT register function:

DRAM data initialization.
This bit is set by software, and it is cleared by hardware. If software sets this bit before the memory controller
is enabled, the controller will automatically initialize DRAM after it is enabled. This bit will be automatically
cleared by hardware once the initialization is completed. This data initialization bit should only be set when
the controller is idle.
0b - There is not data initialization in progress, and no data initialization is scheduled
1b - The memory controller will initialize memory once it is enabled. This bit will remain asserted
until the initialization is complete. The value in DDR_DATA_INIT register will be used to initializememory.

I thinks if we set this bit, only one function is write 0xdeadbeef to dram, so I disable this bit before ddr enable. want to save bootup time about 1440ms by skip this waiting.

/*

     * total memory / bus width = transactions needed

     * transactions needed / data rate = seconds

     * to add plenty of buffer, double the time

     * For example, 2GB on 666MT/s 64-bit bus takes about 402ms

     * Let's wait for 800ms

     */

bus_width = 3 - ((ddr_in32(&ddr->sdram_cfg) & SDRAM_CFG_DBW_MASK)

>> SDRAM_CFG_DBW_SHIFT);

timeout = ((total_mem_per_ctrl_adj << (6 - bus_width)) * 100 /

           (clk >> 20)) << 2;

total_mem_per_ctrl_adj >>= 4;   /* shift down to gb size */

if ((ddr_in32(&ddr->sdram_cfg_2) & SDRAM_CFG2_D_INIT) != 0) {

debug("total size %d GB\n", total_mem_per_ctrl_adj);

debug("Need to wait up to %d ms\n", timeout * 10);

do {

mdelay(10);

        } while (timeout-- > 0 &&

             ((ddr_in32(&ddr->sdram_cfg_2) & SDRAM_CFG2_D_INIT)) != 0);

if (timeout <= 0) {

if (ddr_in32(&ddr->debug[1]) & 0x3d00) {

ERROR("Found training error(s): 0x%x\n",

ddr_in32(&ddr->debug[1]));

            }

ERROR("Error: Waiting for D_INIT timeout.\n");

return -EIO;

        }

   }

but when load bl31 image to dram, it failed, console output stuck when read from sdcard.

NOTICE: 16 GB DDR4, 64-bit, CL=22, ECC on, 256B
NOTICE: Time used by DDR driver 3381 ms
INFO: DDR Controller 1.
INFO: Configuring TrustZone Controller
INFO: Configuring TrustZone Controller
INFO: DDR Controller 2.
INFO: Configuring TrustZone Controller
INFO: Configuring TrustZone Controller
INFO: BL2: Doing platform setup
INFO: BL2: Loading image id 3
INFO: sd-mmc read done.
INFO: sd-mmc read done.
INFO: sd-mmc read done.
INFO: Loading image id=3 at address 0xfbe00000
INFO: sd-mmc read done.

anyone can help me for this issue? thanks!

[yipingwang · Accepted solution]

Controller will write 32 bytes beginning with the address at DDR_INIT_ADDR register during the initialization sequence.

But with ECC enabled, the content of DRAM must be initialized also so the the ECC captured values are correct. In other words, with ECC on if you read a memory location that does not have correct ECC capture value you will get a false ECC error.

[Simon666]

thanks for replay, I change init value from 0xDEADBEEF to 0, system will crash too.

does the init value must be 0xDEADBEEF or some special pattern?

[yipingwang]

Please use non zero value.

This configuration is optional and, if not used, memory will be initialized to all-zeros—the register’s default value.