LS102xA I2C Bus Recovery

[mbend]

Hello,

I am developing a device using the TQMLS102xA module by TQ. My device integrates with several slave devices over a hot-swappable i2c bus, and there are circumstances where an i2c slave device will lock the i2c bus, preventing any writes/reads to any device on the bus.

This comment suggests that the i2c bus recovery functionality can be added to the kernel i2c driver (I believe the LS102xa uses the drivers/i2c/busses/i2c-imx.c i2c implementation).

However,

   a) The linked patch discussion suggests that it will not perform the bus recovery on the LS1021A. Is this correct? Is there any other way of performing the recovery when using an LS1021A?

   b) How can we trigger this bus recovery function from the userspace application using the i2c?

Thanks

Mike

[Pavel]

a)

1) The stuck situation with SCL HIGH.

Stop condition terminates a transfer and can be used to abort it as well.

Therefore if SDA LOW then master should generate pulses on SCL and look for SDA HIGH. As soon as the SDA line will be returned to high level the master can generate STOP condition for abort of transfer.

Usually for this goal the I2C pins should be reconfigured to general open-drain outputs. The software generates pulses on SCL line, look for SDA HIGH and generate STOP condition.

However some devices expect different sequence. For example see please the RESET sequence for Atmel EEPROM (User's Manual of Atmel AT24C01A/02/04/08/16).

MEMORY RESET: After an interruption in protocol, power loss or system reset, any 2-wire part can be reset by following these steps:

1. Clock up to 9 cycles.
2. Look for SDA high in each cycle while SCL is high.
3. Create a start condition.

NXP Reference Manuals for QorIQ processors recommends the following command sequence for Generation of SCL when SDA low

1. Disable the I2C module and set the master bit by setting IBCR to 0x20
2. Enable the I2C module by setting IBCR to 0xA0
3. Read the IBDR
4. Return the I2C module to slave mode by setting IBCR to 0x80

2) The stuck situation with SCL LOW.

If a slave can't receive or transmit another complete byte of data until it has performed some other function, for example servicing an internal interrupt, it can hold the clock line SCL LOW to force the master into a wait state. Data transfer then continues when the slave is ready for another byte of data and releases clock line SCL (Section 7 of I2C-bus specification).

You cannot recover with this situation. The owner of SCL line should release line SCL.

b)

Customers usually use a timer for detection of I2C hanging.

For example, SMB bus is similar to the I2C bus. The I2C Specification recommends 35ms for SMB bus.

-----------------------------------------------------------------------------------------------------------------------
Note: If this post answers your question, please click the Correct Answer button. Thank you!
-----------------------------------------------------------------------------------------------------------------------

[detlef_wolf]

Hi,

I have a similar situation on a custom LS1046A design.

The I2C controller 1 (which has no possibilities to reconfigure the I/Os to GPIO) stuck after an asynchronous reset during a I2C cycle with SDA = low and SCL = high.

I can't power cycle the slave device that caused this, because it is connected to an external power supply.

The recommended sequence to generate clock cycle does not work for unknown reason.

Is there another possibility to create some clock pulses on the SCL line to help the slave device to finish its cycle and to release the SDA line?

Regrads,

Detlef