LS1028A boot (only) RCW from I2C, ATF and u-boot from FSPI

[mikelooijmans]

I've seen some tips on this forum to boot and load the BL2 stage from I2C.

Want we want to do is load the RCW from I2C, and load the remainder from FSPI NOR flash. (Question #1: Is this even possible?)

I tried using the following PBI part in the RCW on the LS1028ARDB:

/* Copy 64k image from FSPI NOR offset 0x9000 to OCRAM (at 0x100000) */
.pbi
blockcopy 0x0f,0x00100000,0x00100000,0x00009000
.end

flashed the resulting .bin into the EEPROM at 0x50.

The FSPI NOR is bootable by itself.

The reason is that we want to switch between low and high power modes (low power means PCIe limited to gen1 and platform bus at 300MHz, while high power runs PCIe at gen3 and platform at 400MHz), and the only way to do so is to change the RCW and reboot.
Doing this in FSPI is doable, but if something goes wrong writing to FSPI the board will be bricked. So we want to put the RCW in I2C EEPROM, so that if things fail, we can always revert to FSPI boot which would always have a working RCW.

[mikelooijmans]

Document AN12028 states:

2. When booting from I2C, refer LS1028A CE document for I2C A-010650.

I've been unable to locate said document "A-010650" anywhere.

[mikelooijmans]

I copied the wrong code, this is what I actually tried:

/* Copy 64k image from FSPI NOR offset 0x9000 to OCRAM (at 0x100000) */
.pbi
blockcopy 0x0f,0x00009000,0x00100000,0x00010000
.end

The previous post had the source and size field exchanged.

[yipingwang]

Change the switch settings and wait for some secs as I2C is lower as compared to Flexspi.

Here are the updated steps:
1. Add the following commands at the end in rcw_1500_gpu600.rcw file
.pbi
write 0x01e00400,0x1800d000
blockcopy 0xa,0x400,0x1800d000,0x9435
.end

CCSR write command:
setting boot location pointer to 0x1800d000 in Boot location pointer low-order address (BOOTLOCPTRL) register present in DCFG.
block copy command:
blockcopy 0x0a,0x400,0x00100000,0x9400
Source : I2C EEPROM = 0xa
Source address: 0x400
Destination address: OCRAM (0x100000)
Block size : size of BL2 binary in bytes

2. Generate the files and program at the respective locations:
3. RCW+PBI binary -- I2C EEPROM at 0x0 (rcw_1500_gpu600.bin)
nxf65210@lsv03611:~/data/work/ls_series/flexbuild_lsdk2108/components/firmware/rcw/ls1028ardb$ make
python3 ../rcw.py -i R_SQPP_0x85bb/rcw_1500_gpu600.rcw -o R_SQPP_0x85bb/rcw_1500_gpu600.bin
(for flexbuild versions before 2108: <flexbuild_dir>/packages/firmware/rcw/ls1028ardb/ R_SQPP_0x85bb/)

4. BL2 binary -- I2C EEPROM at 0x400
nxf65210@lsv03611:~/data/work/ls_series/flexbuild_lsdk2108/components/firmware/atf$ export ARCH=arm64
nxf65210@lsv03611:~/data/work/ls_series/flexbuild_lsdk2108/components/firmware/atf$ export CROSS_COMPILE=aarch64-linux-gnu-
nxf65210@lsv03611:~/data/work/ls_series/flexbuild_lsdk2108/components/firmware/atf$ make distclean
REALCLEAN
nxf65210@lsv03611:~/data/work/ls_series/flexbuild_lsdk2108/components/firmware/atf$ make PLAT=ls1028ardb BOOT_MODE=flexspi_nor pbl RCW=/home/nxf65210/data/work/ls_series/flexbuild_lsdk2108/components/firmware/rcw/ls1028ardb/R_SQPP_0x85bb/rcw_1500_gpu600.bin

bl2.bin present in /flexbuild_lsdk2108/components/firmware/atf/build/ls1028ardb/release/bl2.bin
(for flexbuild versions before 2108: <flexbuild_dir>/packages/firmware/atf/build/ls1028ardb/release)

5. FIP binary -- NOR flash at 0x100000
nxf65210@lsv03611:~/data/work/ls_series/flexbuild_lsdk2108$ flex-builder -c atf -m ls1028ardb -b xspi
(flexbuild_lsdk2004_update_290520/build/firmware/atf/ls1028ardb/fip_uboot.bin)

(for flexbuild versions before 2108: fip.bin present in <flexbuild_dir>/build/firmware/atf/ls1028ardb/)

Programming EEPROM using I2C on U-Boot on LS1028ARDB
=> i2c probe
Valid chip addresses: 00 50 52 53 57 66 67 77 7C
=> i2c write 0xa0000000 0x50 0.2 0x11c
=> i2c read 0x50 0.2 0x114 0xc0000000
=> i2c write 0xa0000000 0x50 0x400.2 <size of bl2.bin>

[mikelooijmans]

This appears to also load the BL2 from the I2C EEPROM, which is not what I want.

Our purpose was to only get the RCW from I2C and then load the BL2 from the SPI NOR flash.

[yipingwang]

Please add the following PBI commands in RCW configuration

.pbi
write 0x01e00400,0x1800d000
blockcopy 0xf,0x9000,0x1800d000,0x10000
.end

For the errata document, please create an internal ticket to require it, you need to sign NDA.

[mikelooijmans]

Added this to the rcw, created a bin and wrote that to the I2C EEPROM at 0x50 on the LS1028ARDB board.

The set the bootswitches to 1010 for I2C boot (also tried 0101 in case I got the orientation wrong).

When I turn on the board the RESET LED turns of, but nothing else happens.

If I set the switches to 1111 for FSPI boot it boots fine.

[yipingwang]

Please only program RCW binary file to I2C EEPROM.

Please deploy bl2_flexspi_nor.pbl at offset 0 on FSPI NOR flash.

[mikelooijmans]

Yes, that's what I did.

[yipingwang]

You can check the POR Status Register where RCW source is selected as I2C, and the contents on OCRAM at 0x18020000 are matched with the RCW+PBI commands of I2C EEPROM. Here is my ccs log:
(bin) 56 % ccs::config_chain {ls1028a dap}
(bin) 57 % display ::ccs::get_config_chain
Chain Position 0: LS1028A
Chain Position 1: CoreSight ATB Funnel
Chain Position 2: CoreSight TMC
Chain Position 3: CoreSight TMC
Chain Position 4: CoreSight ATB Funnel
Chain Position 5: CoreSight ATB Funnel
Chain Position 6: CoreSight ATB Funnel
Chain Position 7: CoreSight ATB Funnel
Chain Position 8: CoreSight CTI
Chain Position 9: CoreSight CTI
Chain Position 10: Cortex-A5
Chain Position 11: Cortex-A5 PMU
Chain Position 12: Cortex-A72
Chain Position 13: CoreSight CTI
Chain Position 14: Cortex-A72 PMU
Chain Position 15: Cortex-A72 ETM
Chain Position 16: Cortex-A72
Chain Position 17: CoreSight CTI
Chain Position 18: Cortex-A72 PMU
Chain Position 19: Cortex-A72 ETM
Chain Position 20: DAP
Chain Position 21: SAP2
(bin) 58 % display ::ccs::read_mem 21 0x1E00000 4 0 0x10
+0 +4 +8 +C
[0x01E00000] 05720FFF DF0FFFFF 00000000 00000000
[0x01E00010] 00000000 00000000 00000000 00000000
[0x01E00020] 000000FF 00000000 00000000 00000000
[0x01E00030] 00000000 00000000 00000000 00000000
(bin) 59 % display ::ccs::read_mem 21 0x18020000 4 0 0x50
+0 +4 +8 +C
[0x18020000] AA55AA55 80100000 3C004010 00000030
[0x18020010] 00000000 00000000 00000000 018F0000
[0x18020020] 0030C000 00000000 00A033A0 00002580
[0x18020030] 00000000 00003296 00000000 00000010
[0x18020040] 00000000 00000000 00000000 00000000
[0x18020050] 00000000 00000000 00000000 00000000
[0x18020060] 00000000 00000000 00000000 00000000
[0x18020070] 000E7000 00000000 BB580000 00000000
[0x18020080] 00000000 00000000 242CA65B 31E00900
[0x18020090] 00000004 31E00400 1800D000 8000000A
[0x180200A0] 00000000 18020000 00000400 80FF0000
[0x180200B0] 00000000 33500890 00800401 334008BC
[0x180200C0] 00000001 33400154 47474747 33400158
[0x180200D0] 47474747 335008BC 00000001 33500154
[0x180200E0] 47474747 33500158 47474747 334008BC
[0x180200F0] 00000000 335008BC 00000000 31E00900
[0x18020100] 00000004 80FF0000 00000000 FFFFFFFF
[0x18020110] FFFFFFFF FFFFFFFF FFFFFFFF FFFFFFFF
[0x18020120] FFFFFFFF FFFFFFFF FFFFFFFF FFFFFFFF
[0x18020130] FFFFFFFF FFFFFFFF FFFFFFFF FFFFFFFF

[mikelooijmans]

How do I do that? I get the impression that I need some specific hardware and/or software?

Would it be possible to have a pre-built I2C RCW binary that works on the LS1028ARDB board? Then I can look at the binaries, find the differences and work from there...

[yipingwang]

Please use i2c_ls1028a.zip and procedure in my previous post, we have verified it on ls1028ardb previously. We don't have good method if not programming BL2.bin in I2C eeprom.

[mikelooijmans]

Now that we found that booting from FSPI won't work anyway with the low-power devices, we'll have to switch to eMMC and the I2C+FSPI boot idea no longer applies..