LS1023 DDR init fail when power on

[George_zheng]

Hi,

We got the problem in our Customer board, When power on display log as below sometimes.

INFO:    RCW BOOT SRC is QSPI

INFO:    RCW BOOT SRC is QSPI

INFO:    Time before programming controller 0 ms

INFO:    Program controller registers

ERROR:   Found training error(s): 0x2100

ERROR:   Error: Waiting for D_INIT timeout.

ERROR:   Writing DDR register(s) failed

ERROR:   Programing DDRC error

ERROR:   DDR init failed

NOTICE:  Incorrect DRAM0 size is defined in platfor_def.h

ERROR:   mmap_add_region_check() failed. error -22

ERROR:   mmap_add_region_check() failed. error -22

NOTICE:  BL2: v1.5(release):

NOTICE:  BL2: Built : 04:11:47, Aug  5 2021

INFO:    Configuring TZASC-380

INFO:    BL2: Doing platform setup

INFO:    BL2: Loading image id 3

INFO:    Loading image id=3 at address 0xbbe00000

Can you provide us with advice and directions for our reference?

We have done in QCVS tool calibation.

[Bulat]

Yes, the log shows that DDR can not start up. You wrote "... When power on display log as below sometimes", what is the log in other times?

Regards,

Bulat

[George_zheng]

The log can boot normal as below

INFO: RCW BOOT SRC is QSPI
INFO: RCW BOOT SRC is QSPI
INFO: Time before programming controller 0 ms
INFO: Program controller registers

NOTICE: 1 GB DDR4, 32-bit, CL=13, ECC off
INFO: Time used by DDR driver 243 ms
NOTICE: BL2: v1.5(release):
NOTICE: BL2: Built : 04:11:47, Aug 5 2021
INFO: Configuring TZASC-380
INFO: BL2: Doing platform setup
INFO: BL2: Loading image id 3
INFO: Loading image id=3 at address 0xbbe00000
INFO: Image id=3 loaded: 0xbbe00000 - 0xbbe0b631
INFO: BL2: Loading image id 5
INFO: Loading image id=5 at address 0x82000000
INFO: Image id=5 loaded: 0x82000000 - 0x8207c6b4
NOTICE: BL2: Booting BL31
INFO: Entry point address = 0xbbe00000
NOTICE: BL31: v1.5(release):
NOTICE: BL31: Built : 02:00:11, Jun 3 2021
NOTICE: Welcome to LS1023 BL31 Phase

U-Boot 2019.10

====================

I check the error when boor abnormal in tfa-layerscape\files\plat\nxp\drivers\ddr\nxp-ddr\ddrc.c

I find the error cause by  the ddr_in32(&ddr->sdram_cfg_2) value can't change form 401010 to 401000

BR,

George

[Bulat]

Do you mean that the same board with the same boot software, can sometimes run normally but sometimes with DDR failure?

[George_zheng]

Hi 

yes

[Bulat]

Many reasons can result in such a floating error. These can be bad contacts after soldeing, unstable power supplies, incorrect DDR reset circuitry, DDR settings close to allowed margins. Try to check these issues. Make sure that u-boot settings of DDR and QCVS ones are the same.

[George_zheng]

Hi,

I find the error cause by D_int can't clear by HW.

Check the D_int in ref. manual.

DRAM data initialization.
This bit is set by software, and it is cleared by hardware. If software sets this bit before the memory
controller is enabled, the controller will automatically initialize DRAM after it is enabled. This bit will be
automatically cleared by hardware once the initialization is completed. This data initialization bit should
only be set when the controller is idle.
0b - There is not data initialization in progress, and no data initialization is scheduled
1b - The memory controller will initialize memory once it is enabled. This bit will remain asserted
until the initialization is complete. The value in DDR_DATA_INIT register will be used to initialize
memory.

How to debug the D_int reg. when HW how to clear?

[Bulat]

D_INIT bit is a visible part of the problem. The proccessor can not initialize the DDR controller due to mistakes during internal automatic calibration procedures, as a result the memory can not be read/written and D_INIT bit stays '1'. Nnormally it is cleared after the whole memory is overwritten/initialized.

Auto-calibration can not be debugged. Any of issues I listed earlier can result in such a floating mistake.