LS1017 - XSPI_B read errors

[Stefan_L]

Hello NXP Support Team,

I have a read issue with the XSPI_B interface of the LS1017 device.

Hardware Info/Setup:

• CPU XSPI_B is connected to a microsemi FPGA
• CPU platform frequency = 400 MHz, CPU speed = 1500 MHz --> XSPI Errata A-050568 is not applicable
• Single point-to-point connection (tracelength around 70mm, matched to +-2mm)
• DDR Mode 50 MHz (100Mbit)
• Only IP-Mode Commands are used for LS1017
• DQS is driven by FPGA - provided read strobe(MCR0[RXCLKSRC]==3)
• DLL for DQS sampling point set to: SLVDLYTARGET=0xF ; DLLEN=0x1 ; OVRDEN=0x0 ; Other fields in DLLxCR kept as reset value (all zero)
• Only CS-Signal has a 4.75k pullup resistor
• The simulated signal integrity on PCB level looks fine

Error/Test-Funcion:

Initially a testfuction on the LS1017 (VxWorks operating system) generates a random pattern and writes it once to the a test memory within the FPGA.

After the write transaction has finished the funcion reads the pattern periodically from the FPGA test memory an compares it to the original values (512 Bytes per read loop).

Attached you can find an example console output of my test funcion showing the error.

I tried to read and verify the test memory content 5000 times. In this case the first 1207 runs showed no errors. Run 1208 contained errors.

The error pattern has conspicuous features:

• Errors occure 64 Byte aligned (=IP-Command length) --> (attached example: offset 384/64=6)
• Error is exactly 64 Byte long (=IP-Command length) --> (attached example: offset 448-384=63
• Within the 64 error bytes only every second byte has errors --> falling edge of DQS?
• It appers that the second bytes are shifted for the whole 64 bytes

Offset 384-391 expected:	0x d5 79 23 80 52 56 5e 4d
Offset 384-391 actual:	0x d5 8a 23 79 52 80 5e 56

For other testfuncion runs the errors have the same features, but at different runs + offsets.

My Questions:

1. Have you seen similar read issues in the past 
2. In the Reference Manual Figure 187. DQS is drawn in phase with A_SCLK/B_SCLK, but in reality DQS rising/falling edge is shifted by round-trip-time + FPGA lead time. (in our case in the magnitude of 8 to 10 ns). Can you provide more information on how internal DQS sampling mechanism / DLL delay line is working? (e. g. timebase for DLL)
3. Datasheet Table 49. contains a formula for CS output hold time/ CS output delay with the parameter T/2. T is the period of FSCK previous mentioned in the same table? FSCK = serial root clock? --> in our case T=10ns?
4. Datasheet Figure 32.: FlexSPI DDR mode 2 = (MCR0[RXCLKSRC]=0x3)? TFSIDVW Value from Table 48 ist also applicable to DDR mode with MCR0[RXCLKSRC]=0x3

Best regards

SL

[Hector_Villarruel]

Hello @Stefan_L 

Hope this email finds you well,

This may be a synchronization issue,

I would like to ask you a few questions,

Did you consider the note from the section?:

18.5.14.4 DLL configuration for sampling:

If serial root clock is lower than 100 MHz, DLL is unable to lock on half cycle of serial root clock because the delay
cell number is limited in delay chain. Then DLL should be configured as following instead:
— OVRDEN=0x1
— OVRDVAL=N; Each delay cell in DLL is about 75 ps~225 ps. The delay of DLL delay chain is (N *
Delay_cell_delay), N should be set based on max. DDR frequency that current project supported, N =
17,please notice this is a recommended value. May need to adjust in real application if facing failure.
— Other fields in DLLxCR should be kept as reset value (all zero)

Could you please provide us with the root clock signals waveforms from the LS1017?

Did you consider the information from the section "18.6.6 Application on FPGA device " from the QorIQ LS1028A Reference Manual, Rev. 0, 12/2019? 

Have a great day.

BR,

Hector V