LS1012A-RDB eMMC flash

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LS1012A-RDB eMMC flash

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bgreen
Contributor II

I'd like to set up the eMMC flash on the LS1012A-RDB. I've set the DIP switch to select the eMMC flash on SDHC2 but after booting up I get the error:

mmc1: Controller never released inhibit bit(s).

This message scrolls forever. The SD card on SDHC1 works fine. This is using the LS1012A SDK Rev 0.4

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bgreen
Contributor II

I have discovered the source of my problem. When originally setting up QSPI bank 2, I copied over the RCW and u-boot from QSPI bank 1. These images are from the BHR ASK (I assume). I then loaded u-boot, kernel, and ppa images from the SDK, but not the RCW. Not loading the correct RCW was the source of my problem. After loading the SDK RCW (PBL_0x35_0x08_800_250_1000_default.bin) the eMMC flash came up correctly.

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bgreen
Contributor II

I have discovered the source of my problem. When originally setting up QSPI bank 2, I copied over the RCW and u-boot from QSPI bank 1. These images are from the BHR ASK (I assume). I then loaded u-boot, kernel, and ppa images from the SDK, but not the RCW. Not loading the correct RCW was the source of my problem. After loading the SDK RCW (PBL_0x35_0x08_800_250_1000_default.bin) the eMMC flash came up correctly.

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ufedor
NXP TechSupport
NXP TechSupport

> I've set the DIP switch to select the eMMC flash

What exactly you have done?

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bgreen
Contributor II

On the LS1012A-RDB there is an LS1012A with 2 SDHC interfaces. SDHC2 is connected to a mux which can select between several different on-board devices using a DIP switch. I have set the switch to:

MUX_SDHC2_S1: 1
MUX_SDHC2_S0: 0

According to the manual this should connect SDHC2 to the onboard eMMC flash. Using the images provided in the SDK I get the error mentioned above.

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ufedor
NXP TechSupport
NXP TechSupport

What is the component schematics name printed on the PCB, what are the switches positions?

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bgreen
Contributor II

CPU: LS1012A+ SKT LGA 211

3x MUX: 74CBTLV3253DS

eMMC: MTFC4GACAAAM-1M WT

DIP Switches (From left to right on the board)

DIP SW1: 0b11100100

DIP SW2: 0b01000010

In Particular the ones dealing with the eMMC flash are:

MUX_SDHC2_S1: 1
MUX_SDHC2_S0: 0

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ufedor
NXP TechSupport
NXP TechSupport

> MUX_SDHC2_S1: 1
> MUX_SDHC2_S0: 0

To which DIP SW these settings corresponds?

Please provide a clear photo of the switches.

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bgreen
Contributor II

DIPSW.png

These are the switches on the board, except the settings are (from left to right):

11100100 01000010

Where 1 is up and 0 is down.

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ufedor
NXP TechSupport
NXP TechSupport

Which configuration is on the photo?

Which switches you have altered?

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bgreen
Contributor II

Shown in the Image:

10100110 00000000

Default that ships with the board:

11100100 00000000

Current board settings:

11100100 01000010

The first two bits of the second switch connect SDHC2 to the eMMC flash, the last two bits of the second switch select booting from the second bank of QSPI flash.

From the default setup that ships with the board I have changed the bit labeled MUX_SDHC2_S1 from 0 to 1, and the bit labeled MUX_QSPI_S0 from 0 to 1.

From the switches in the image the differences are:

SW_ENG_USE: 0 -> 1

UART_MUX_EN_B: 1 -> 0

MUX_SDHC2_S1: 0 -> 1

MUX_QSPI_S0: 0 -> 1

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ufedor
NXP TechSupport
NXP TechSupport

> From the default setup that ships with the board I have changed the bit

> labeled MUX_SDHC2_S1 from 0 to 1, and the bit labeled MUX_QSPI_S0 from 0 to 1.

Please clarify this statement because default setup for these bits is 00.

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bgreen
Contributor II

The defaults are 0 and 0. I changed them both to 1. Changing MUX_SDHC2_S1 should let me use the eMMC flash. Changing MUX_QSPI_S0 lets me boot from the second QSPI flash bank.

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