How to configure TBI for eTSEC2 (TWR-LS1021A)

[romitchatterjee]

Hello,

I am writing an Ethernet device driver for the LS1021A Tower board, running a custom OS. The documentation says that to enable TBI for any port other than eTSEC1, the MIIM register base address has to be changed accordingly. My question is is this valid only for the eTSEC_MDIO_MIIMCFG register, or all MIIM registers (e.g. eTSEC_MDIO_MIIMCOM)? For example, if I enable TBI for eTSEC2, eTSEC_MDIO_MIIMCFG register address to be used will 2D2_5520 (instead of eTSEC1's 2D2_4520), but eTSEC_MDIO_MIIMCOM register address to be used will be 2D2_4524 or 2D2_5524?

Some help please?

[romitchatterjee]

Thanks for the help :smileyhappy:. SGMII interfaces are now up if I check it through the MDIO interface. But if I check the TBI status register, it shows that the interface is down. Is there any procedure to check the status of SerDes module? Do I need to set anything in SerDes module or somewhere else?

[romitchatterjee]

I am still waiting for the reply.

If I check status register of external PHY, then it shows that link is up. However, if I check status register of TBI, it shows (value 0x0149) link is not up. Do you have any idea about the root cause of this issue?

[bpe]

Unlike earlier, PowerPC core based devices, LS1021A has all on-chip
SGMII PCS's connected to a single MDIO interface controlled from the set of
registers at the offset 2D2_4000.