How to change IFC target from NAND Flash to CPLD in U-Boot for LS1046A

[2sanghaesea]

Hello,

We are working with a custom board based on the LS1046ARDB.

In our design:

We boot from eMMC, and do not use QSPI NOR flash.

The pins originally connected to QSPI NOR flash on the LS1046ARDB are instead connected to an FPGA on our custom board.

The IFC CS1 region, which is used for NAND flash on the LS1046ARDB, is what we would like to reassign to a CPLD in our custom board.

We tried modifying ls1046ardb.h in the U-Boot source to replace the NAND configuration with settings for our CPLD, but it didn’t work as expected.

Is there a proper way to reassign or remap the IFC CS1 region from NAND to another peripheral like a CPLD in U-Boot for the LS1046A?

Are there additional changes required beyond the board header file (e.g., IFC configuration, or RCW)?

Any guidance would be appreciated.

Best Regards

/*
 * NAND Flash Definitions
 */
#define CONFIG_NAND_FSL_IFC
#endif

#define CONFIG_SYS_NAND_BASE        0x7e800000
#define CONFIG_SYS_NAND_BASE_PHYS   CONFIG_SYS_NAND_BASE

#define CONFIG_SYS_NAND_CSPR_EXT    (0x0)
#define CONFIG_SYS_NAND_CSPR    (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
                | CSPR_PORT_SIZE_8  \
                | CSPR_MSEL_NAND    \
                | CSPR_V)
#define CONFIG_SYS_NAND_AMASK   IFC_AMASK(64 * 1024)
#define CONFIG_SYS_NAND_CSOR    (CSOR_NAND_ECC_ENC_EN   /* ECC on encode */ \
                | CSOR_NAND_ECC_DEC_EN  /* ECC on decode */ \
                | CSOR_NAND_ECC_MODE_8  /* 8-bit ECC */ \
                | CSOR_NAND_RAL_3   /* RAL = 3 Bytes */ \
                | CSOR_NAND_PGS_4K  /* Page Size = 4K */ \
                | CSOR_NAND_SPRZ_224    /* Spare size = 224 */ \
                | CSOR_NAND_PB(64)) /* 64 Pages Per Block */

#define CONFIG_SYS_NAND_ONFI_DETECTION

#define CONFIG_SYS_NAND_FTIM0       (FTIM0_NAND_TCCST(0x7) | \
                    FTIM0_NAND_TWP(0x18)   | \
                    FTIM0_NAND_TWCHT(0x7) | \
                    FTIM0_NAND_TWH(0xa))
#define CONFIG_SYS_NAND_FTIM1       (FTIM1_NAND_TADLE(0x32) | \
                    FTIM1_NAND_TWBE(0x39)  | \
                    FTIM1_NAND_TRR(0xe)   | \
                    FTIM1_NAND_TRP(0x18))
#define CONFIG_SYS_NAND_FTIM2       (FTIM2_NAND_TRAD(0xf) | \
                    FTIM2_NAND_TREH(0xa) | \
                    FTIM2_NAND_TWHRE(0x1e))
#define CONFIG_SYS_NAND_FTIM3       0x0

#define CONFIG_SYS_NAND_BASE_LIST   { CONFIG_SYS_NAND_BASE }
#define CONFIG_SYS_MAX_NAND_DEVICE  1
#define CONFIG_MTD_NAND_VERIFY_WRITE

#define CONFIG_SYS_NAND_BLOCK_SIZE  (128 * 1024)

/*
 * CPLD
 */
#define CONFIG_SYS_CPLD_BASE        0x7fb00000
#define CPLD_BASE_PHYS          CONFIG_SYS_CPLD_BASE

#define CONFIG_SYS_CPLD_CSPR_EXT    (0x0)
#define CONFIG_SYS_CPLD_CSPR        (CSPR_PHYS_ADDR(CPLD_BASE_PHYS) | \
                    CSPR_PORT_SIZE_8 | \
                    CSPR_MSEL_GPCM | \
                    CSPR_V)
#define CONFIG_SYS_CPLD_AMASK       IFC_AMASK(64 * 1024)    //250826 64 -> 512 130mm2 Settings
#define CONFIG_SYS_CPLD_CSOR        CSOR_NOR_ADM_SHIFT(16)

/* CPLD Timing parameters for IFC GPCM */
#define CONFIG_SYS_CPLD_FTIM0       (FTIM0_GPCM_TACSE(0x0e) | \
                    FTIM0_GPCM_TEADC(0x0e) | \
                    FTIM0_GPCM_TEAHC(0x0e))
#define CONFIG_SYS_CPLD_FTIM1       (FTIM1_GPCM_TACO(0xff) | \
                    FTIM1_GPCM_TRAD(0x3f))
#define CONFIG_SYS_CPLD_FTIM2       (FTIM2_GPCM_TCS(0xf) | \
                    FTIM2_GPCM_TCH(0xf) | \
                    FTIM2_GPCM_TWP(0x3E))
#define CONFIG_SYS_CPLD_FTIM3       0x0

/* IFC Timing Params */
#define CONFIG_SYS_CSPR0_EXT        CONFIG_SYS_NAND_CSPR_EXT
#define CONFIG_SYS_CSPR0        CONFIG_SYS_NAND_CSPR
#define CONFIG_SYS_AMASK0       CONFIG_SYS_NAND_AMASK
#define CONFIG_SYS_CSOR0        CONFIG_SYS_NAND_CSOR
#define CONFIG_SYS_CS0_FTIM0        CONFIG_SYS_NAND_FTIM0
#define CONFIG_SYS_CS0_FTIM1        CONFIG_SYS_NAND_FTIM1
#define CONFIG_SYS_CS0_FTIM2        CONFIG_SYS_NAND_FTIM2
#define CONFIG_SYS_CS0_FTIM3        CONFIG_SYS_NAND_FTIM3

#define CONFIG_SYS_CSPR2_EXT        CONFIG_SYS_CPLD_CSPR_EXT
#define CONFIG_SYS_CSPR2        CONFIG_SYS_CPLD_CSPR
#define CONFIG_SYS_AMASK2       CONFIG_SYS_CPLD_AMASK
#define CONFIG_SYS_CSOR2        CONFIG_SYS_CPLD_CSOR
#define CONFIG_SYS_CS2_FTIM0        CONFIG_SYS_CPLD_FTIM0
#define CONFIG_SYS_CS2_FTIM1        CONFIG_SYS_CPLD_FTIM1
#define CONFIG_SYS_CS2_FTIM2        CONFIG_SYS_CPLD_FTIM2
#define CONFIG_SYS_CS2_FTIM3        CONFIG_SYS_CPLD_FTIM3

[yipingwang]

Please modify the following section according to the correct CS on your custom board.

#define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_CPLD_CSPR_EXT
#define CONFIG_SYS_CSPR2 CONFIG_SYS_CPLD_CSPR
#define CONFIG_SYS_AMASK2 CONFIG_SYS_CPLD_AMASK
#define CONFIG_SYS_CSOR2 CONFIG_SYS_CPLD_CSOR
#define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_CPLD_FTIM0
#define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_CPLD_FTIM1
#define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_CPLD_FTIM2
#define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_CPLD_FTIM3

In addition, please modify the section "CPLD Timing parameters for IFC GPCM" according to your custom board.