Compile kernel in the ls-5.15.71-2.2.0_distro In the LLDPUG_RevL5.15.71-2.2.0, it seems when do some reconfiguration in the kernel, rootfs should be repack to finish the change. Here will generate kernel without repack the roofts in the Linux host machine just compile the kernel.

The SerDes tool is a part of the QorIQ Configuration and Validation Suite (QCVS) product. This document will illustrate how to use the tools to validate the SerDes on the LS1046ARDB SerDes1 Lane1(Lane C) without Oscilloscope and BERT(Bit Error Ratio Tester). It validate the LS1046ARDB SerDes1 Lane1 with digital loopback, external loopback and external mode.

Basic Concept of Secure boot on LS1028A Platform Build secure boot ATF image Generate secure boot CSF headers for Linux tiny itb image Deploy secure boot images on the target board Blow OTPMK fuse in u-boot and through CodeWarrior CCS Write SRK hash keys to the mirror registers through CCS Secure boot Trouble Shooting  

The attached patch adds error detection for A53 and A57 cores. Hardware error injection is supported on A53. Software error injection is supported on both. For hardware error injection on A53 to work, proper access to L2ACTLR_EL1, CPUACTLR_EL1 needs to be granted by EL3 firmware. This is done by making an SMC call in the driver. Failure to enable access disables hardware error injection. For error interrupt to work, another SMC call enables access to L2ECTLR_EL1. Failure to enable access disables interrupt for error reporting. CPU Memory Error Syndrome and L2 Memory Error Syndrome registers can be used for checking L1 and L2 memory errors. However, only A53 supports double-bit error injection to L1 and L2 memory. This driver uses the hardware error injection when available, but also provides a way to inject errors by software. Both A53 and A57 supports interrupt when multibit errors happen. To use hardware error injection and the interrupt, proper access needs to be granted in ACTLR_EL3 (and/or ACTLR_EL2) register by EL3 firmware SMC call. Correctable errors do not trigger such interrupt. This driver uses dynamic polling internal to check for errors. The more errors detected, the more frequently it polls. Combining with interrupt, this driver can detect correctable and uncorrectable errors. However, if the uncorrectable errors cause system abort exception, this driver is not able to report errors in time.

How to use UART2 instead of UART1 on LS1043ARDB/LS1046ARDB.   1. Compile PBL binary from RCW source file 2. Compile U-Boot binary 3. Compile TF-A binaries (bl2_.pbl and fip.bin) 4. Program TF-A binaries on specific boot mode     1-COMPILE PBL BINARY FROM RCW SOURCE FILE   You have to create a new directory to compile the binaries that you need to create a TF-A binary You need to compile the rcw_<boot_mode>.bin binary to build the bl2_<boot_mode>.pbl binary.   Clone the rcw repository and compile the PBL binary.   1. $ git clone https://github.com/nxp-qoriq/rcw 2. $ cd rcw 3. $ cd ls1043ardb 4. $ make   Inside the directory called “RR_FQPP_1455” you can see some binaries with the next nomenclature: rcw_<freq>.bin Where “freq” is the frequency in MHz of the processor, the values of the frequency are 1200MHz, 1400MHz, 1500MHz, and 1600MHz   2-COMPILE U-BOOT BINARY You need to compile the u-boot.bin binary to build the fip.bin binary. Clone the U-boot repository and compile the U-Boot binary for TF-A   1. $ git clone https://github.com/nxp-qoriq/u-boot 2. $ cd u-boot 3. $ git checkout -b LSDK-21.08 LSDK-21.08 4. $ export ARCH=arm64 5. $ export CROSS_COMPILE=aarch64-linux-gnu- 6. $ make distclean 7. $ nano configs/ls1043ardb_tfa_defconfig 7.1 change the bootargs "console=ttyS0,115200" for "console=ttyS1,115200" 7.2 add "CONFIG_CONS_INDEX=2 7. $ make ls1043ardb_tfa_defconfig 8. $ make   3 Compile TF-A binaries (bl2_.pbl and fip.bin) 1. $ git clone https://github.com/nxp-qoriq/atf 2. $ cd atf 3. $ git checkout -b LSDK-21.08 LSDK-21.08 4. $ export ARCH=arm64 5. $ export CROSS_COMPILE=aarch64-linux-gnu- 6. $ nano plat/nxp/common/include/default/ch_3_2/soc_default_base_addr.h 6.1 Change the line "#define NXP_UART_ADDR 0x021C0000" for "#define NXP_UART_ADDR 0x021D0000" 6.2 Change the line "#define NXP_UART1_ADDR 0x021D0000" for "#define NXP_UART_ADDR 0x021C0000" 7. $ nano plat/nxp/common/include/default/ch_2/soc_default_base_addr.h 7.1 Change the line "#define NXP_UART_ADDR 0x021C0500" for "#define NXP_UART_ADDR 0x021C0600" 7.2 Change the line "#define NXP_UART1_ADDR 0x021C0600" for "#define NXP_UART_ADDR 0x021C0500"   The compiled BL2 binaries, bl2.bin and bl2_<boot mode>.pbl are available at atf/build/ls1043ardb/release/. NOTE: For any update in the BL2 source code or RCW binary, the bl2_<boot mode>.pbl binary needs to be recompiled   3.1 HOW TO COMPILE BL2 BINARY To compile the BL2 binary without OPTEE: make PLAT=<platform> bl2 BOOT_MODE=<boot_mode> pbl RCW=<path_to_rcw_binary>/<rcw_binary_for_specific_boot_mode> To LS1043ARDB for SD boot: make PLAT=ls1043ardb bl2 BOOT_MODE=sd pbl RCW=<path_to_rcw_binary>/<rcw_freq.bin> To LS1043ARDB for NOR boot: make PLAT=ls1043ardb bl2 BOOT_MODE=nor pbl RCW=<path_to_rcw_binary>/<rcw_freq.bin> To LS1043ARDB for NAND boot: make PLAT=ls1043ardb bl2 BOOT_MODE=nand pbl RCW=<path_to_rcw_binary>/<rcw_freq.bin>   3.2 HOW TO COMPILE FIP BINARY   To compile the FIP binary without OPTEE and trusted board boot: $make PLAT=<platform> fip BL33=<path_to_u-boot_binary>/u-boot.bin   For LS1043ARDB: $make PLAT=ls1043ardb fip BL33=<path_to_u-boot_binary>/u-boot.bin   The compiled BL31 and FIP binaries ( bl31.bin, fip.bin ) are available at atf/build/ls1043ardb/release/. For any update in the BL31, BL32, or BL33 binaries, the fip.bin binary needs to be recompiled.   4 Program TF-A binaries on specific boot mode For that step you can use a tftp server, but it is easier with a USB formatted on FAT32.   You have to put the files “ bl2_<boot_mode>.pbl” and “fip.bin” in the usb and follow the steps to your boot mode.   4.1 Program TF-A binaries on IFC NOR flash For LS1043A, the steps to program TF-A binaries on IFC NOR flash are as follows:   1. Boot the board from the default bank. 2. Under U-boot prompt: => usb start 3. Flash bl2_nor.pbl: => fatload usb 0:1 $load_addr bl2_nor.pbl a. Alternate bank: => protect off 64000000 +$filesize && erase 64000000 +$filesize && cp.b $load_addr 64000000 $filesize b. Current bank: => protect off 60000000 +$filesize && erase 60000000 +$filesize && cp.b $load_addr 60000000 $filesize 4. Flash fip.bin: => fatload usb 0:1 $load_addr fip.bin a. Alternate bank: => protect off 64100000 +$filesize && erase 64100000 +$filesize && cp.b $load_addr 64100000 $filesize b. Current bank: => protect off 60100000 +$filesize && erase 60100000 +$filesize && cp.b $load_addr 60100000 $filesize 5. Reset your board: a. Alternate bank: cpld reset altbank b. Current bank: cpld reset   4.2 Program TF-A binaries on NAND flash   1. Boot the board from the default bank. 2. Under U-boot prompt: => usb start 3. Flash bl2_nand.pbl to NAND flash: => fatload usb 0:1 $load_addr bl2_nand.pbl => nand erase 0x0 $filesize;nand write $load_addr 0x0 $filesize; 4. Flash fip_uboot.bin to NAND flash: => fatload usb 0:1 $load_addr fip.bin => nand erase 0x100000 $filesize;nand write $load_addr 0x100000 $filesize; 5. Reset your board: => cpld reset nand   4.3 Program TF-A binaries on SD card   To program TF-A binaries on an SD card, follow these steps:   1. Boot the board from the default bank. 2. Under U-boot prompt: => usb start 3. Flash bl2_sd.pbl to SD card: => fatload usb 0:1 $load_addr bl2_sd.pbl => mmc write $ load_addr 8 A1 4. Flash fip.bin to SD card: => fatload usb 0:1 $load_addr bl2_sd.pbl => mmc write $load_addr 800 A1 5. Reset your board: => cpld reset sd Now the console should be out from UART2 port of the board.  

On the LS1046ARDB, there are 2 1G SGMII with PHY, but sometimes customer want to get PHY-less connection to evaluate the performance, so they may have to change the non-fixed link properties into fixed-link by reconfiguration the SW configuration. In this document, it will give details of configuring the LS1046ARDB to support the fixed-link requirement with LSDK2108 focus on the DTS and Linux kernel. The ethernet MAC in this document is FM1 mEMAC6: 1AE_A000h. Because there is no PHY-less connection on board. We only provide the status when the MAC has been configured.

When customer only has SD/eMMC on the customer board, when they don’t have CWTAP in hand, how do they boot the customer board(bare board) after the board come back from the factory for the first time. This document describes the steps how to use the CMSIS-DAP in this situation as a reference for user.

CMSIS-DAP is a useful tool and exists in some NXP reference boards, but how to use it. This document describes the steps how to use the CMSIS-DAP in the LS1034ARDB as a reference for user.

On the LX2160ARDB, there are 2 25G SFP interfaces, but no 10G SFP interface. When customer want to test the 10G SFPs to evaluate the performance, they have to change the 25G SFP interfaces into 10G by reconfiguration the SW configuration. In this document, it will give details of configuring the LX2160ARDB to support the customer’s 10G SFP interfaces requirement with LSDK2108. At the end, an image will be generated to deployed into the SD card. Because SD card is a convenient way boot up LX2160ARDB, if one wrong move could brick the system, the customer could unplug the SD card to repeat the steps below.

ENETC is a PCI Integrated End Point(IEP). IEP implements peripheral devices in an SoC such that software sees them as PCIe device. ENETC is an evolution of BDR(Buffer Descriptor Ring) based networking IPs. Key goal of the DPDK is to provide a simple, complete framework for fast packet processing in data plane applications. Using the APIs provided as part of the framework, applications can leverage the capabilities of underlying network infrastructure.DPDK been prominent software in user space for networking applications pushes for eNetc driver to be written in user space. This document introduces overview of the NXP ENETC and how its driver is implemented and integrated into the DPDK. DPDK eNetc Driver support features queue start/stop, MTU update, promisc, Unicast and multicast MAC filtering, rss hash, crc offload, vlan offload, Rx checksum offload, basic stats. 1. ENETC Hardware Introduction 2. LS1028 Default ENETC Driver 3. User Space eNetc Driver design 4. DPDK eNetc Driver support features 5. Setup DPDK applications over ENETC platform

This document introduces how to configure software to disable the second DDR controller and only use DDR1 on LX2160A platforms, includes configuring RCW to disable clock of DDR2 by using DEVDISR register and setting HN-F SAM control registers to disable DDR2 in CodeWarrior and atf software coding. 1. Configure RCW to Disable clock of DDR2 by using DEVDISR register 2. Configuring HN-F SAM control register to disable DDR2 in CodeWarrior 3. ATF coding to configure HN-F SAM control register to disable the specific DDR controller

UEFI (Unified Extensible Firmware Interface) describes an interface between the operating system (OS) and the platform firmware. The interface consists of data tables that contain platform-related information, plus boot and runtime service calls that are available to the operating system and its loader. Together, these provide a standard, modern environment for booting an operating system and running pre-boot applications. 1. UEFI boot flow 2. Build UEFI firmware images on the host PC 3. Generate Composite Firmware with UEFI Firmware Images 4. Deploy LSDK distro boot with UEFI

This document uses LS1043AQDS as an example to introduce how to use attaching method to debug atf and u-boot on QorIQ LS ARM 64 bit target boards with CodeWarrior for ARMv8. 1. Build ATF and U-boot with Debugging information Enabled in LSDK 2. Debug BL2 in ATF with CodeWarrior for ARMv8 3. Debug BL31 in ATF with CodeWarrior for ARMv8 4. Debugging u-boot with CodeWarrior for ARMv8

Quick start to recover a ATF in a damaged storage device. In this case, a blanked LS1012AFRWY QSPI, which is the only BL2 and FIP storage device on board, is restored using CW TAP, CW 4NET and Flex-Installer. Download firmware using flex-installer   nxplayerscape@nxp-global-cas:~/Downloads/josephs-downloads/Flex-Installer-LDP$ flex-installer -i download -f firmware_ls1012afrwy_qspi.boot Please specify correct '-m <machine>' Valid machine name: ls1012ardb ls1012afrwy ls1021atwr ls1028ardb ls1043ardb ls1046ardb ls1046afrwy ls1088ardb_pb ls2088ardb lx2160ardb_rev2 lx2162aqds  imx6qpsabresd imx6qsabresd imx6sllevk imx7ulpevk imx8mmevk imx8mnevk imx8mpevk imx8mqevk imx8qmmek imx8qxpmek imx8ulpevk  nxplayerscape@nxp-global-cas:~/Downloads/josephs-downloads/Flex-Installer-LDP$ flex-installer -i download -f firmware_ls1012afrwy_qspi.boot -m ls1012afrwy    Downloading http://www.nxp.com/lgfiles/sdk/sdk2110/firmware_ls1012afrwy_qspi.boot ...   % Total    % Received % Xferd  Average Speed   Time    Time     Time  Current                                  Dload  Upload   Total   Spent    Left  Speed   0     0    0     0    0     0      0      0 --:--:-- --:--:-- --:--:--     0 -rw-rw-r-- 1 nxplayerscape nxplayerscape 0 abr  6 13:27 firmware_ls1012afrwy_qspi.boot    Downloading http://www.nxp.com/lgfiles/sdk/sdk2110/boot_LS_arm64_lts_5.10.tgz ...   % Total    % Received % Xferd  Average Speed   Time    Time     Time  Current                                  Dload  Upload   Total   Spent    Left  Speed 100  342M  100  342M    0     0  5695k      0  0:01:01  0:01:01 --:--:-- 5752k    Downloading http://www.nxp.com/lgfiles/sdk/sdk2110/rootfs_sdk2110_ubuntu_main_arm64.tgz ...   % Total    % Received % Xferd  Average Speed   Time    Time     Time  Current                                  Dload  Upload   Total   Spent    Left  Speed 100  809M  100  809M    0     0  5641k      0  0:02:26  0:02:26 --:--:-- 3109k Downloaded distro images [Done] nxplayerscape@nxp-global-cas:~/Downloads/josephs-downloads/Flex-Installer-LDP$ flex-installer -i download -f firmware_ls1012afrwy_qspiboot.img Please specify correct '-m <machine>' Valid machine name: ls1012ardb ls1012afrwy ls1021atwr ls1028ardb ls1043ardb ls1046ardb ls1046afrwy ls1088ardb_pb ls2088ardb lx2160ardb_rev2 lx2162aqds  imx6qpsabresd imx6qsabresd imx6sllevk imx7ulpevk imx8mmevk imx8mnevk imx8mpevk imx8mqevk imx8qmmek imx8qxpmek imx8ulpevk  nxplayerscape@nxp-global-cas:~/Downloads/josephs-downloads/Flex-Installer-LDP$ flex-installer -i download -f firmware_ls1012afrwy_qspiboot.img -m ls1012afrwy    Downloading http://www.nxp.com/lgfiles/sdk/sdk2110/firmware_ls1012afrwy_qspiboot.img ...   % Total    % Received % Xferd  Average Speed   Time    Time     Time  Current                                  Dload  Upload   Total   Spent    Left  Speed 100 1617k    0 1617k    0     0  1529k      0 --:--:--  0:00:01 --:--:-- 1529k -rw-rw-r-- 1 nxplayerscape nxplayerscape 1656690 oct 25  2021 firmware_ls1012afrwy_qspiboot.img boot_LS_arm64_lts_5.10.tgz already exists rootfs_sdk2110_ubuntu_main_arm64.tgz already exists Downloaded distro images [Done] Create a PBL project   Note: Need to create a custom board connection based on: How to create a CWTAP to LS Series Processors JTAG-Link. Try to dump 16 MB of memory.   Look for downloaded firmware   Flash it to qspi using flash programmer.   Press the reset button on LS1012AFRWY. Doesn't need to disconnect CWTAP.   Hope this helps when no storage device has a valid binary to get to U-boot, when a board is running U-Boot or Tiny Distro, it can update any SW easily. Ask any questions you may have. Best regards, Joseph

Introduction.   CodeWarrior TAP combined with a host debugger provide control and visibility into your target embedded system through a debugging process. Main tasks to test a Reference Design Board with are: Flash an storage device for userspace debugging and recovering a board. RCW and PBL configuration. DDR and SerDes configuration. DDR and SerDes validation. U-Boot and Kernel debug For all of them and every activity involving real hardware, a link is needed nevertheless is a very straightforward process that is going to be crawled in this document.   Hardware List.   CodeWarrior TAP USB cable. USB A-Mini-B. CodeWarrior TAP TIP CWH-CTP-CTX10-YE. COP connector. CodeWarrior TAP Base Unit. CWH-CTP-BASE-HE. Host computer. Processor: Windows® OS: Intel® Pentium® 4 processor, 2 GHz or faster, Intel® Xeon™, Intel® Core™, AMD Athlon™ 64, AMD Opteron™, or later Linux® OS: 1.8 GHz Intel® Pentium® class processor (or better). 64-bit host OS required. Operating System: Microsoft® Windows 7 64-bit Microsoft® Windows 10 64-bit RHEL 7.8, 8.2 64-bit CentOS 7.8, 8.2 64-bit Ubuntu 16.04 64-bit Ubuntu 18.04 64-bit Ubuntu 20.04 64-bit Fedora 31 64-bit Mint 19.3 64-bit Memory. At least 2 GB of RAM At least 3 GB of free disk space NXP Reference Board featuring. LS2088A. LS1012A. LS1043A. LS1088A. LS1046A.   Power-up set-up.   Connect debugger and target's end to each other, while both of them are powered off. Connect TAP TIP multipin connector to TAP multipin socket pushing them.     Ribbon cable red side has to be on TIP pin 1 side and Target COP pin 1 side, look for CPU/Processor silkscreen and pin 1 label. See below examples.            Note that CPU JTAG silkscreen label is in the red box, but also may be visible the 1 label. Power up CWTAP. The most efficient way to set up CWTAP is using USB cable, due to can be both powered and communicated with just one cable. Connect USB to Host PC and wait for TX LED to go green blinking.     If communication is directly to host, considerate that you'll be joined into a private network and you will not have internet access. Power up Target. Connect target to DC supply and turn on power switch and press reset button (needed for boards which don't have a power switch). Create a connection in CodeWarrior.   Open CodeWarrior previously previously set up and with a workspace selected. Make sure that Target Connections window is visible, if not, look for it in Window > Show view > Other.   Every target connection desired has to be based on CW predefined board connections. Predefined connections are processor oriented and have a default configuration, you cannot and should not override this values, e.g., MAC field for TAP probe, you should duplicate and then customize it. Click on the reference board that you have, then duplicate, name new target and save.     Double click or click edit to enter TAP MAC value. Settings are initialized based on the duplicated board, it's recommended to just update MAC. Click on look for probes, select the one that matches your MAC and save.     Save. Serial number field is updated and you are notified of unsaved changes, is the asterisk at the left of your duplicate name, save (ctrl + s) and you may close the connection data is done now.     Open a project or create a new one. I created a new project to simply read RCW inside NOR Flash Bank 0 of LS1043ARDB following the below process.         Then, open Connections View to test the new connection based on custom connection data created before. Click on recheck connection button (green play button) and connection status should change from no-link (connection button right side) to connection working.     Diagnose connection.   Go to Target Connections view and click diagnose connection, Connection Diagnostics view should be popped up and log different tests to ensure that there is a target connection and SOC modules are accessible.     At this point, the connection is made and is already tested, but in this document, RCW will also be dumped into our project just to work ourselves with the connection already made. Under Component Inspector view go to Import tab, select Import From Target and click Read from target.     Results are display in text box as: RCWSR registers were successfully read from the target and imported! RCWSR1:0x08100010 RCWSR2:0x0A000000 RCWSR3:0x00000000 RCWSR4:0x00000000 RCWSR5:0x14550002 RCWSR6:0x80004012 RCWSR7:0xE0025000 RCWSR8:0xC1002000 RCWSR9:0x00000000 RCWSR10:0x00000000 RCWSR11:0x00000000 RCWSR12:0x00038800 RCWSR13:0x00000000 RCWSR14:0x00001101 RCWSR15:0x00000096 RCWSR16:0x00000001 That should save a connection to a CWTAP to reuse with that same MAC intended to a any RDB that features the selected processor. Later on you can recover LS Series processors, flash, configure or validate a board. Please ask any question you may have. Best regards, Joseph

How to bring up a card when the flash is blank, or the image is corrupted. How to boot cards from various boot mode when changed the RCW as requirements. This documentation will use LS1046ARDB as new board to realize the functions (all target board in the document is LS1046ARDB). Content Bring up LS1046A with CodeWarrior TAP Boot up from the SD card Compile PBL binary from RCW source file Compile the PBL binary into firmware Program the firmware into the target board (LS1046ARDB) Boot up from the QSPI Compile firmware from RCW source file Program the firmware into the target board (LS1046ARDB) Boot up from the eMMC Enable the on board eMMC Compile firmware from RCW source file Program the firmware into the target board (LS1046ARDB)

The BareMetal framework targets to support the scenarios that need low latency, real-time response, and high-performance. There is no OS running on the cores and customer-specific application runs on that directly. This document describes how to develop customer-specific application based on BareMetal framework. The directory “app” stored in u-boot repository includes the use cases for testing GPIO, I2C, IRQ init, QSPI, Ethernet, USB, PCIe, CAN, ENETC and SAI features. 1. GPIO use case 2. I2C use case 3. IRQ use case 4. QSPI Use case 5. Ethernet use case 6. USB Use case 7. PCIe use case 8. CAN Use Case 9. ENETC Use Case 10. SAI Use Case 11. Build and Run the Baremetal Application

1. FMan VSP Hardware Overview 2. The usage of Virtual Storage Profiles 3. FMan VSP Driver 4. Traffic bifurcation using VSP on LS1046ARDB

1. Fuse Provisioning Utility Introduction 2. Input File for Fuse Provisioning Tool 3. Build Fuse Provisioning Firmware Image with flex-builder and Deploy the Firmware Image 4. Build and Deploy Fuse Provisioning Image Manually 5. Validate Fuse Provisioning

This document introduces basic concept of Power Management, LS1028 RCW configuration to enable GPIO, Linux Kernel source and device tree modification to support GPIO wakeup, Kernel configuration to enable sleep feature and GPIO wakeup driver, export GPIO pin and enable interrupt, Order system to sleep and trigger GPIO interrupt to wake up the system.