When creating a static library project, it is necessary to select a specific target MCU (for example LPC1768 or LPC1114/301).
However this selection primarily controls the compiler/assembler options (for example Cortex-M3 or Cortex-M0). This contrasts with "application projects" where the target MCU also controls linker options (in particular the linker script used when generating the final executable) as well as the debug connection settings.
Sometimes you may want to create a static library project which can be used on multiple different MCUs without being rebuilt. Where the MCUs are in the same family (for example LPC1758 and LPC1768), this is normally straightforward - typically just choose any MCU within the MCU family.
Where the MCUs are in different families (for example LPC1768 and LPC1343, which both use Cortex-M3), then in some cases it may still be possible to produce a library project suitable for use on all the MCUs of interest. However typically in such cases, much more care is required to ensure differences in peripherals, associated LPCOpen or CMSIS projects, etc. will not impact on the libraries functionality.
In extreme cases, it is actually possible to generate libraries that may work for MCUs based on different CPUs. This may be achieved in a couple of ways.
First of all, it is possible to create a different built configuration for each CPU/MCU - by modifying the target CPU in the compiler/assembler properties for each build configuration. Again care is required because of differences in peripherals, associated LPCOpen or CMSIS projects etc.
Secondly, you could simply create a library project which uses the "lowest common denominator" MCU. Thus a library created for a Cortex-M0 based part may also be usable on a Cortex-M3 based part (again allowing for differences in peripherals, LPCOpen or CMSIS projects, etc). This is because the instruction set used by Cortex-M0 is a subset of that for Cortex-M3. However the reverse does not apply - a Cortex-M3 targeted library will not be suitable for use on a Cortex-M0 based part.