timer with two interrupt flags

[jimdeas]

On the LPC24xx, how can I manage high rate interrupts for both MR0 and CR1? (Same VIC_TIMER1 address)

I have an application using CR0 as a clock source MR0 to reset that counter and CR1 to detect an async signal. As long as CR1 never fires the primary counter is flawless. Once I add CR1 and change the interrupt to steer the interrupt based on T1IR_bit(CR1INT or MR0int) I appear to lose some of the interrupts.

I am checking both bits in a attempt to service interrupts that happen while I am already in the interrupt routine but that does not seem to keep me from losing interrupts. I.E.

Void INT_TIMER(){

while( CR1INT | MR0INT){

   if CR1INT (do work, CR1INT=1)

   if MR0INT (do work, MR0INT =1)

}

VICADDRESS=0

reti

}

[jimdeas]

Tried clearing the flag at the start of the INTR but the interrupts are async in nature. Ended up just using the interrupt that triggers at the highest rate along with a non-interrupt 'capture' to service both in the same routine. Nothing else seemed stable.

[CarlosCasillas]

Hi Jim,

That seems to be happening because the application is triggering a second interrupt while the interrupt service routine is being executed (and it already asked for the flags); therefore, it will be possible that just one of the sentences will be executed, clearing the interrupt flags after its competition, avoiding re-entering to the same interrupt by other flags.

So, as a workaround you could try clearing the interrupt flag at the beginning of the ISR, and maybe restructuring the logic of the code allowing multiple calls to the ISR without repeating the actions of a previously executed task.

Hope this will be useful for you.
Best regards!
/Carlos
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