lpc1768 watch dog timer

[Sathiya]

Hi,

I am using LPC1768 watch dog timer, how can we determine to find out the Selectable time period  (TWDCLK × 232 × 4) and also  i configure mode register to enable the WDT. when we use the RESET bit in WDMOD.  

[xiangjun_rong · Accepted solution]

Hi,

From the following Figs, you can see that the WDT tick source can befrom irc_clk, PCLK and rtc_clk.

The nominal irc_clk is 4MHz , pls refer to section 4.3.1 Internal RC oscillator in UM10360.pdf

The rtc_clk is 1Hz which is generated by 32KHz crystal.

The PCLK for WDT is determined by the selection of register PCLKSEL0[PCLK_WDT], this is the setting, in other words:

PCLKSEL0[1:0]=00 in binary, CCLK/4 is selected.

PCLKSEL0[1:0]=01 in binary, CCLK is selected.

PCLKSEL0[1:0]=10 in binary, CCLK/2 is selected.

PCLKSEL0[1:0]=11 in binary, CCLK/8 is selected.

Pls refer to section 4.7.3 Peripheral Clock Selection registers 0 and 1 (PCLKSEL0 -
0x400F C1A8 and PCLKSEL1 - 0x400F C1AC)

Table 42. Peripheral Clock Selection register bit values
PCLKSEL0 and PCLKSEL1
individual peripheral’s clock
select options
Function Reset
value
00 PCLK_peripheral = CCLK/4 00
01 PCLK_peripheral = CCLK
10 PCLK_peripheral = CCLK/2
11 PCLK_peripheral = CCLK/8,

For the CCLK frequency, pls refer to the PLL0 configuration and the post divider. Pls refer to Fig 7. Clock generation for the LPC176x/5x.

Hope it can help you

BR

XiangJun Rong