Dear @Harry_Zhang
Thank you for your answer.
We use the LPC55S69 with the clock connected to PLL0, which runs at 150MHz and normally, we have kCLOCK_DivAhbClk set to 1. When we want to write to flash, we set kCLOCK_DivAhbClk to 2 to have the CPU running at 75MHz, which is functional.
In this case, the fsl_iap functions should check on kCLOCK_BusClk, because then it differs from kCLOCK_CoreSysClk.
Kind regards,
Folkert