UART + DMA: how to ?

[haiomaio3]

From the specification exert below, I understand, that setting FIFO enable to 1, enables also the DMA Mode. Does it mean the DMA Mode operates "automatically"? I cannot see a relationship, that I have to configure the DMA in some way. In other ways, how should I read the below specification regarding operating or not with DMA? How do you interpret the specification?

"UARTn FIFO Control Register

Bit    Symbol

0       FIFO Enable           0/1  Active high enable for both UARTn Rx and TX FIFOs and UnFCR[7:1] access.
                                               This bit must be set for proper UART operation. Any transition on this bit will
                                               automatically clear the related UART FIFOs.

3       DMA Mode                   When the FIFO enable bit (bit 0 of this register) is set, this bit selects the DMA
                                               mode

4.6.1 DMA Operation
The user can optionally operate the UART transmit and/or receive using DMA. The DMA
mode is determined by the DMA Mode Select bit in the FCR register. This bit only has an
affect when the FIFOs are enabled via the FIFO Enable bit in the FCR register.

UART receiver DMA

In DMA mode, the receiver DMA request is asserted on the event of the receiver FIFO
level becoming equal to or greater than trigger level, or if a character timeout occurs."

---

UM10360
LPC17xx User manual
Rev. 01 — 4 January 2010

[jeremyzhou]

Hi Hai Maio,

Thank you for your interest in NXP Semiconductor products and
for the opportunity to serve you.
To implement the UART DMA, it needs to configure the GPDMA module besides the UART module, and I've attached the demo project which describes how to use UART in DMA mode, please refer to it for details.

Have a great day,
TIC

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[haiomaio3]

Hei,

I open a second issue on the same topic, but I cannot find the issue listed in the forum anymore. Hence, the copy of the issue here as question once more:

In the specification, the possible values for the DMA Mode are not listed, as for example for FIFO enable 0/1. Is this an error in the specification, or it is a way to say something not written ? How do you interpret the missing values? and the DMA Mode description?

"UARTn FIFO Control Register

Bit    Symbol

0       FIFO Enable           0/1  Active high enable for both UARTn Rx and TX FIFOs and UnFCR[7:1] access.
                                               This bit must be set for proper UART operation. Any transition on this bit will
                                               automatically clear the related UART FIFOs.

3       DMA Mode                   When the FIFO enable bit (bit 0 of this register) is set, this bit selects the DMA
                                               mode

[wschmidt324]

You mean, it should have been stated, that the bit is only read only ?!?

[jeremyzhou]

Hi Hai Maio,

Thanks for your reply.

1）That the bit is only read-only ?!?
-- The FIFO Enable and DMA Mode bits are able to read and write.

Have a great day,
TIC

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[jeremyzhou]

Hi Hai Maio,

Thanks for your reply.
That's not an error or missing in the specification, as I pointed out in the last reply. To implement the UART DMA, it needs to configure the GPDMA module besides the UART module. It means that the developer needs to review the GPDMA module to learn how to configure GPDMA combine with the UART.

Have a great day,
TIC

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Note:
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