The code in M0 core is running from SRAM or FLASH? (LPC54114)

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The code in M0 core is running from SRAM or FLASH? (LPC54114)

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da_chen
Contributor II

I'm now running a dual-core project in LPC54114. Every thing works fine. But it came to me that from where the M0 core fetched its code? SRAM or FLASH? What about M4?

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ZhangJennie
NXP TechSupport
NXP TechSupport

Hi Chen,

The M0+ core slave project is distributed in RAM. The slave project is associated with the master project. So, it will be compiled first and then the image data will be linked into the master image file.

So after power on, the slave fetch code from flash to RAM then run code from RAM.

The M4 core run project from Flash.


Have a great day,
Jun Zhang

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ZhangJennie
NXP TechSupport
NXP TechSupport

Hi Chen,

The M0+ core slave project is distributed in RAM. The slave project is associated with the master project. So, it will be compiled first and then the image data will be linked into the master image file.

So after power on, the slave fetch code from flash to RAM then run code from RAM.

The M4 core run project from Flash.


Have a great day,
Jun Zhang

-------------------------------------------------------------------------------
Note:
- If this post answers your question, please click the "Mark Correct" button. Thank you!

- We are following threads for 7 weeks after the last post, later replies are ignored
Please open a new thread and refer to the closed one, if you have a related question at a later point in time.
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