Hi Jeremy,
Thank you very much for the consistent support from your side reagrding the SDRAM interface issue.
I am able to interface AS4C4M16SA-C&I" 64M – (4M x 16 bit) Synchronous DRAM (SDRAM) with LPC4367. I have tried a lot but after going going through the application note AN11508 and under standing the behaviour and conection required for interface i made some modifcation in the code which is mentioned below.
the major modification which enable me to interface SDRAM and access it properly is making the feedback clock conficguration for both the clock pin in case of LPC4367 as per the application note. In other controllers loke LPC546xx there is a provision for configuring the feed back clock source which is also mentioned in the data in basic configuration information whihc is missing in case of LPC43XX i guess.
/* SDRAM_CLK0 (EMC_CLK0)*/
Chip_SCU_ClockPinMuxSet(0, ( SCU_MODE_INACT | SCU_MODE_ZIF_DIS | SCU_MODE_INBUFF_EN | SCU_MODE_HIGHSPEEDSLEW_EN | SCU_MODE_FUNC5));
/* SDRAM_CLK2 (EMC_CLK3)*/
Chip_SCU_ClockPinMuxSet(2, ( SCU_MODE_INACT | SCU_MODE_ZIF_DIS | SCU_MODE_INBUFF_EN | SCU_MODE_HIGHSPEEDSLEW_EN | SCU_MODE_FUNC5));
This information is no where mentioned in the datasheet or user manual of LPC4367. This was the inout which i got from application not.
I am wondering how come your code is functional with the previous project which you share? Sicne after this modifcation only iwas able to access and read write the memory. I also checked with other SDRAM chip MT48LC16M16A2_TIG
Also reagarding the configureation i need to do some small modifications mentioned below
static const IP_EMC_DYN_CONFIG_T AS4C4M16SA_CI_Config ={
EMC_NANOSECOND(64000000 / 4096), /* Row refresh time (RefreshPeriod)*/
0x01, /* Dynamic Memory Read Configuration*/
EMC_NANOSECOND(18), /*< Precharge Command Period */
EMC_NANOSECOND(42), /*< Active to Precharge Command Period */
EMC_NANOSECOND(70), /*!< Self Refresh Exit Time */
EMC_CLOCK(1), /*!< Last Data Out to Active Time */
EMC_CLOCK(5), /*!< Data In to Active Command Time */
EMC_NANOSECOND(12), /*!< Write Recovery Time */
EMC_NANOSECOND(60), /*!< Active to Active Command Period */
EMC_NANOSECOND(60), /*!< Auto-refresh Period */
EMC_NANOSECOND(70), /*!< Exit Self Refresh */
EMC_NANOSECOND(12), /*!< Active Bank A to Active Bank B Time */
EMC_CLOCK(2), /*!< Load Mode register command to Active Command */
{
{
/*!< Device Configuration array with SDRAM Mode register*/
EMC_ADDRESS_DYCS0, /* Base Register*/
3, /* RAS */
/* Mode Register value*/
EMC_DYN_MODE_WBMODE_PROGRAMMED |
EMC_DYN_MODE_OPMODE_STANDARD |
EMC_DYN_MODE_CAS_3 |
EMC_DYN_MODE_BURST_TYPE_SEQUENTIAL |
EMC_DYN_MODE_BURST_LEN_8,
/* Device Config [0]*/
EMC_DYN_CONFIG_DATA_BUS_16 |
EMC_DYN_CONFIG_LPSDRAM |
EMC_DYN_CONFIG_4Mx16_4BANKS_12ROWS_8COLS |
EMC_DYN_CONFIG_MD_SDRAM
},
{0, 0, 0, 0}, /* Device Config [1]*/
{0, 0, 0, 0}, /* Device Config [2]*/
{0, 0, 0, 0} /* Device Config [3]*/
}
};
After doing the modification mentioned above in bold and changing the configurations i an able to verify the SDRAM code.
But still will again confirm after i redesign the development board with proper cconnection. Hope it shpild work there as well since it s working with 20Mhz frequency above which it is not working. I guess there is routing iissue as per the application note which we need to redesign as per the instrcutio mentioned in the Applicaton note.
Thanks
Gaurav More