Resetting LPC546xx while writing to external static RAM

[vijo]

Hi there,

ref. LPC546xx datasheet fig.25 External static memory read/write access

Does a low on the reset pin abort an external write cycle - if going low in the WR5 window - with a chance for leaving garbage in the addressed SRAM location?

Or will the reset action be delayed until the writecycle has finished?

Just short - is the action of a low reset asynchronous or synchronous with what the CPU is actually doing.

Best regards

Viggo

[xiangjun_rong]

Hi, Viggo,

If you clear the EMCSYSCTRL[EMCRD] bit, both the POR RESET event and the Reset Pin/Watchdog Reset events can reset the EMC module.

If you set the EMCSYSCTRL[EMCRD] bit, only the POR RESET event can reset the EMC module, The Reset pin/Watchdog reset events can not reset the EMC module in the condition.

Once the EMC module is reset, all registers and functions of the EMC are initialized to it's Reset states immediately, in other words, the Reset event is asynchronous with the CPU action.

Have a great day,
TIC

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[vijo]

thank you for the information TIC,

will a reset of the EMC module immediately abort a memory write cycle to a external SRAM ?

regards

Viggo

[xiangjun_rong · Accepted solution]

Hi, Viggo,

Yes, a reset event of the EMC module immediately aborts a memory write cycle to a external SRAM.

BR

Xiangjun Rong