@Alice_Yang
The pwm pulse is not generated, please update me if there are any changes in the configuration below
int main()
{
* 1 */ SYSCON->SYSAHBCLKCTRL0 |= 1 << 25 ;// Enables clock for CTIMER0.
/* 2 */ SYSCON->PRESETCTRL0 |= 1 << 25; // CTIMER reset control // Clear the CTIMER reset.
/* 3 */ // Pins: Select timer pins through switch matrix.
/* 4 */ // SWM0->PINASSIGN_DATA[4] | ;
SYSCON->SYSAHBCLKCTRL0 |= 1<<7; //Enables clock for switch matrix
SWM0->PINASSIGN.PINASSIGN4 = 0X18;// P0_24 PIN SELECTED
SYSCON->SYSAHBCLKCTRL0 |= 0<<7; //DISABLE clock for switch matrix
/* 5 */ CTIMER->TCR |= 1 << 1;/*Enabled. The Timer Counter and the Prescale Counter are synchronously reset on the
next positive edge of the APB bus clock. The counters remain reset until TCR[1] is
returned to zero*/
CTIMER->PR = 0xFFFFFFFFU;
/* 6 */ CTIMER->MCR |= 1 << 0 | 1 << 1; // Interrupt on MR0: an interrupt is generated when MR0 matches the value in the TC
// Reset on MR0: the TC will be reset if MR0 matches it. 0 = disabled. 1 = enabled
/* 7 */ CTIMER->MR[0] =100;//Timer counter match value
/* 8 */ CTIMER->MSR[0]=100; //Timer counter match shadow value
// START COUNT
/* 9 */ CTIMER->PWMC |= 0<<1;//PWM. PWM mode is enabled for CTIMER_MAT0.
/* 10 */ CTIMER->TCR |= 1<<0 | 1<<1;// Enabled. The Timer Counter and Prescale Counter are enabled.
//Enabled. The Timer Counter and the Prescale Counter are synchronously reset on the
//next positive edge of the APB bus clock. The counters remain reset until TCR[1] is
//returned to zero
// while(1)
// {
/* 7 */ CTIMER->MR[1] =50;//Timer counter match value
/* 8 */ CTIMER->MSR[1]=50; //Timer counter match shadow value
// }
}
