LPC55S69 - LPADC Clock Frequency - CFG[PWRSEL] Dependent

[PhilV]

Hi, I am trying to find out about the LPADC clock speed restrictions, and how they are affected by the CFG{PWRSEL] setting.

In the peripheral configuration tool "Power Level" for the ADC0 has 4 options, described (not very helpfully) as "Lowest", "Next Lowest", "Next Highest" and "Highest".
The tool tip gives a little more information:

Inspecting the register through the Peripheral register view gives very similar "help":

The User Manual (Rev. 2.4 — 8 October 2021) states:

However the datasheet for LPC55S6x (Rev 2.4 8 December 2022) only shows the following:

So even here I can only see that 24MHz max is mentioned, and that note 11 says if I want to use the temperature sensor I have to slow the clock to 6MHz.

So;

1. What affect does changing the CFG[PWRSEL] value have, and how should the clock speed be adjusted in relation?
2. Does 24MHz ADCK provide 1Msample/s?
3. If so what effect does slowing the clock to 6MHz have so that the temperature sensor can be used?

Similarly ADC power consumption is only give for CFG[PWRSEL] = 0; how do I determine what effect setting to other power levels would have (on either the power consumption or the conversion rate?):

[xiangjun_rong · Accepted solution]

Hi,

As the following fig, till now, the PWRSEL bits have to be set up as 00 in binary, the other setting are reserved.

The ADC driving clock frequency is set up as 24MHz at most,

For the ADC conversion rate, I suppose that you can use the formula to figure out:

ADC Conversion rate = ADC clock frequency / (Sample clocks + Conversion clocks)

The ADC clock frequency is 24Mhz at most

The Sample clocks is defined in the STS bits in CMDH[1:15]

The conversion clocks is as following:

In 12-bit mode conversions. The conversion time is 17.5 ADC clocks,

In 16-bit mode conversions. The conversion time is 20.5 ADC clocks.

The value of Power Enable PWREN in CFG register is set to 1.

Hope it can help you

BR

XiangJun Rong