Lpc1857 double writes to memory

[lpcware]

Content originally posted in LPCWare by enyi on Sat Feb 15 08:33:30 MST 2014
Hi
My problem is double writes to memory when ever i do a single write to a memory address.

For example if do following write function

uint8_t *ptr = 0x1C000000;

*ptr =0x00;

This results in following:

0x1C000000 = 0x00

0x1C000020 = 0x00

This second write to the address 4 bytes after original intended address occurs at the same time.

Does anyone know how to fix this problem or do i need to use the lpc4357 instead

Thanks

[lpcware]

Content originally posted in LPCWare by enyi on Sun Feb 23 12:18:33 MST 2014

I am trying to write to IS61WV5128BLL-10  SRAM (512K X 8).

Code that I used which causes this double write to external SRAM is in the attached file "Double Memory Write problems.txt

The debug memory output is shown in debug_memory.png

Enyi

[lpcware]

Content originally posted in LPCWare by enyi on Sun Feb 23 12:10:49 MST 2014
test

Best Regards

Enyi

[lpcware]

Content originally posted in LPCWare by enyi on Sun Feb 16 00:53:42 MST 2014
Thanks Martin,

I will follow your suggestions, simplify the code and will get a screen shot of memory output and I will post it later.

Best Regards

Enyi

[lpcware]

Content originally posted in LPCWare by capiman on Sun Feb 16 00:40:48 MST 2014
Hi,
ok, code looks now better.
I see in main that putpixel is called once with x=100 and x=100.

fbptr8bit is initially 0x1C000000
After going through first loop it is increased by decimal 480 * 100 * 4 = 192000, resulting fbptr8bit is now 0x1C02EE00.
After going through second loop it is increased by decimal 100 * 4 = 400, resulting fbptr8bit is now 0x1C02EF90.

Now you do 4 accesses:

  *fbptr8bit++ = (uint8_t) 0x00;
          *fbptr8bit++ = (uint8_t) 0x00;
  *fbptr8bit++ = (uint8_t) 0x00;
  *fbptr8bit++ = (uint8_t) 0x00;

I am not familiar with memory setup of LPC1857, but I think you shall even at least see 4 accesses:
- One to 0x1C02EF90
- One to 0x1C02EF91
- One to 0x1C02EF92
- One to 0x1C02EF93

I don't know, how it looks like e.g. when you do a byte access, if 2 or 4 bytes are read, before 2 or 4 bytes are written with one byte updated.
But I think you shall see at least 4 write accesses with addresses in the area from 0x1C02EF90 to 0x1C02EF93.

Initially you have written a different example, single access to 0x1C000000. Why have you changed to more difficult example with putpixel.
If the easy example is not yet working, it is useless to use more complicated example.

If you go back to easy example, have you checked the other parts beside addresses, like OE, (BLS0), CS0, WE, D0...D7?
What values do they have, Can you see that with different content the D0...D7 is changing? Changing in both accesses?
Both accesses are write accesses (check WE)? Both read accesses (check OE)? Both go to your memory chip (CS0)?

Have you compared with other examples that your memory setup is equal to them? Have you looked
if the values you set into registers match the values you want described in User Manual?

Best regards,

Martin

[lpcware]

Content originally posted in LPCWare by enyi on Sat Feb 15 13:10:46 MST 2014
Hi capiman,


I have attached the correct code without the typo's in it.
The code does compile ok.

I am not making this double write issue up, it does actually happen


Thanks

[lpcware]

Content originally posted in LPCWare by capiman on Sat Feb 15 12:53:49 MST 2014
No, there is init_SRAM() which is different.
Also open and closing brackets don't match. At least after while(1) in main, there is missing a '}'...
Therefore I think your code is not compiling at all and you are hunting ghosts.

[lpcware]

Content originally posted in LPCWare by enyi on Sat Feb 15 12:50:24 MST 2014
Hi Capiman,


init_sram () is in the file attachment and it comes straight after

/*-----------------------------------------------------------------------------
  Main Loop End
----------------------------------------------------------------------------*/

[lpcware]

Content originally posted in LPCWare by capiman on Sat Feb 15 12:42:04 MST 2014
Can you tell me where I find init_sram().
It is not contained in the code...

[lpcware]

Content originally posted in LPCWare by enyi on Sat Feb 15 12:17:40 MST 2014
Hi Capiman


I have attached the full main code and the code does compile without any errors.


Thanks

[lpcware]

Content originally posted in LPCWare by capiman on Sat Feb 15 12:09:54 MST 2014
I think there is some error in the posted code? Perhaps wrong content posted?

There is no main().

There is code outside of any function (call of putpixel).

It is in the text of your posting as well as in attached *.txt file.

Have you checked if you can compile the code at all without an error?

[lpcware]

Content originally posted in LPCWare by enyi on Sat Feb 15 10:34:53 MST 2014
Hi TheFallGuy


Thanks for replying so quickly


I have put my code in the attached filed for you to look at.

Thanks

[lpcware]

Content originally posted in LPCWare by enyi on Sat Feb 15 10:05:54 MST 2014
Hi TheFallGuy


Thanks for replying so quickly


I have copied the code for initializing  external SRAM ( 512KB X 8 bits) and writing a pixel to the frame buffer at 0x1C000000 .


void init_SRAM (void)
{
//  External Memory Controller Definitions
/*----------------------------------------------------------------------------*/

uint32_t *ptr;
uint32_t *ptrdata;



/*----------------------------------------------------------------------------
  Initialize external memory controller
*----------------------------------------------------------------------------*/




/* Select and enable EMC branch clock */
// CLK_M3_EMC_CFG is connect to BASE_M3_CLK (PPL1 180MHZ) to used only with SRAM
LPC_CCU1->CLK_M3_EMC_CFG  = CCU_CLK_CFG_AUTO | CCU_CLK_CFG_RUN;
while (!(LPC_CCU1->CLK_M3_EMC_STAT & CCU_CLK_STAT_RUN))


  /* Configure EMC port pins */


  scu_pinmux(0x1,0,MD_PLN_FAST,FUNC2);  /* P1_0:  A5                          */
  scu_pinmux(0x1,1,MD_PLN_FAST,FUNC2);    /* P1_1:  A6                          */
  scu_pinmux(0x1,2,MD_PLN_FAST,FUNC2);    /* P1_2:  A7                          */
  scu_pinmux(0x1,3,MD_PLN_FAST,FUNC3);    /* P1_3:  OE                          */
//scu_pinmux(0x1,4,MD_PLN_FAST,FUNC3);    /* P1_4:  BLS0                        */
  scu_pinmux(0x1,5,MD_PLN_FAST,FUNC3);    /* P1_5:  CS0                         */
  scu_pinmux(0x1,6,MD_PLN_FAST,FUNC3);    /* P1_6:  WE                          */
  scu_pinmux(0x1,7,MD_PLN_FAST,FUNC3);    /* P1_7:  D0                          */
  scu_pinmux(0x1,8,MD_PLN_FAST,FUNC3);    /* P1_8:  D1                          */
  scu_pinmux(0x1,9,MD_PLN_FAST,FUNC3);    /* P1_9:  D2                          */
  scu_pinmux(0x1,10,MD_PLN_FAST,FUNC3);   /* P1_10: D3                          */
  scu_pinmux(0x1,11,MD_PLN_FAST,FUNC3);   /* P1_11: D4                          */
  scu_pinmux(0x1,12,MD_PLN_FAST,FUNC3);   /* P1_12: D5                          */
  scu_pinmux(0x1,13,MD_PLN_FAST,FUNC3);   /* P1_13: D6                          */
  scu_pinmux(0x1,14,MD_PLN_FAST,FUNC3);   /* P1_14: D7                          */

  scu_pinmux(0x2,0,MD_PLN_FAST,FUNC2);    /* P2_0:  A13                         */
  scu_pinmux(0x2,1,MD_PLN_FAST,FUNC2);    /* P2_1:  A12                         */
  scu_pinmux(0x2,2,MD_PLN_FAST,FUNC2);    /* P2_2:  A11                         */
  scu_pinmux(0x2,6,MD_PLN_FAST,FUNC2);    /* P2_6:  A10                         */
  scu_pinmux(0x2,7,MD_PLN_FAST,FUNC3);    /* P2_7:  A9                          */
  scu_pinmux(0x2,8,MD_PLN_FAST,FUNC3);    /* P2_8:  A8                          */
  scu_pinmux(0x2,9,MD_PLN_FAST,FUNC3);    /* P2_9:  A0                          */
  scu_pinmux(0x2,10,MD_PLN_FAST,FUNC3);   /* P2_10: A1                          */
  scu_pinmux(0x2,11,MD_PLN_FAST,FUNC3);   /* P2_11: A2                          */
  scu_pinmux(0x2,12,MD_PLN_FAST,FUNC3);   /* P2_12: A3                          */
  scu_pinmux(0x2,13,MD_PLN_FAST,FUNC3);   /* P2_13: A4                          */


  scu_pinmux(0x6,7,MD_PLN_FAST,FUNC1);    /* P6_7:  A15                         */
  scu_pinmux(0x6,8,MD_PLN_FAST,FUNC1);    /* P6_8:  A14                         */


  scu_pinmux(0xd,15,MD_PLN_FAST,FUNC2);   /* PD_15: A17                         */
  scu_pinmux(0xd,16,MD_PLN_FAST,FUNC2);   /* PD_16: A16                         */

  scu_pinmux(0xe,0,MD_PLN_FAST,FUNC3);    /* PE_0:  A18                         */


  LPC_EMC->CONTROL  = 0x00000001;     /* EMC Enable                         */
  LPC_EMC->CONFIG   = 0x00000000;     /* Little-endian, Clock Ratio 1:1     */



 
  /* Static memory configuration (chip select 0)                              */

  LPC_EMC->STATICCONFIG0  =
                            (0 <<  0) | // MW [1:0] = 0 (8 bit Memeory Width)
            (0 <<  3) | // PM = 0  Page Mode disabled
                         (0 <<  6) | // PC = 0  Active Low Chip Select
            (1 <<  7) | // PB = 1 Byte lane state (All BLS High for Read / Must be 1 to use WE signal
            (0 <<  8) | // EW = 0 Disabled extended wait
                            (0 <<  19)|  // B = 0  Disabled Buffer
                            (0 <<  20) ; // P = 0  Disabled Write Protect


  LPC_EMC->STATICWAITOEN0 = 0x1 ; // 1 NO Delay (Selects the delay from chip select n or address change, whichever is later, to output enable)
  LPC_EMC->STATICWAITWEN0 = 0x0 ; // 0 1 EMC_CCLK Cylce delay (180MZ = 5.55r ns) (Selects the delay from chip select n to write enable.)
  LPC_EMC->STATICWAITRD0  = 0x4 ; //  4 EMC_CCLK Cylce delay (180MZ = 5.55r ns) (Selects the delay from chip select n to a read access)
  LPC_EMC->STATICWAITPAG0 = 0x0 ; //  0 Page Mode Previously disabled (180MZ = 5.55r ns) (Selects the delay for asynchronous page mode sequential accesses for chip select n.)
  LPC_EMC->STATICWAITWR0  = 0x4 ; // 0x4 4 EMC_CCLK Cylce delay (180MZ = 5.55r ns * 4) (Selects the delay from chip select n to a write access.)
  LPC_EMC->STATICWAITTURN0 = 0x4 ; // 0 1 EMC_CCLK Cylce (180MZ = 5.55r ns) (Selects bus turnaround cycles.)

}


#define BASE_ADDR 0x1C000000 // 2Mb (512K x 8bit) SRAM







LPC_LCD->UPBASE = BASE_ADDR; // Set upper base address to SRAM base address



putpixel(100, 100,GuiConst_PIXEL_ON);



uint8_t *fbptr8bit = (uint8_t *)BASE_ADDR;



/************************ Local auxiliary functions ***************************/

void putpixel(uint32_t x, uint32_t y, uint32_t val){
//fbptr[x+y*480] = (uint32_t) 0x00000000;
uint32_t i;
uint32_t j;


fbptr = (uint32_t *) BASE_ADDR;
fbptr8bit = (uint8_t *) BASE_ADDR;


for(j=0;j<480*y;j++){
fbptr8bit++;
fbptr8bit++;
fbptr8bit++;
fbptr8bit++;

}

  for(i=0;i<x;i++){
fbptr8bit++;
fbptr8bit++;
fbptr8bit++;
fbptr8bit++;
}


*fbptr8bit++ = (uint8_t) 0x00;
        *fbptr8bit++ = (uint8_t) 0x00;
*fbptr8bit++ = (uint8_t) 0x00;
*fbptr8bit++ = (uint8_t) 0x00;


}

[lpcware]

Content originally posted in LPCWare by TheFallGuy on Sat Feb 15 09:35:45 MST 2014
There must be a bug in your code as no processor will do a double write unless you code it to do so. Suggest you post your code, so we can see what you have done wrong.