LPC84x Flash memory access time

[Andy_G]

Is there any further information available on the trade-offs/issues for changing the flash memory access time (FLASHTIM in the FLASHCFG register).

The following is taken from the LPC84x User Manual (UM11029 Rev 1.7)

The reset value is the longest access time. Does this give the most stability over the full temperature range? Does it improve the power consumption?

[frank_m]

Flash access time is related to core clock frequency.
For higher clock frequencies, you need wait states, i.e. a greater value for said Flash access time.
Higher junction temperatures usually aggravate timing issues. A symptom of such problems are seemingly random crashes / hardfaults.

The relation between Flash access time and core clock should be described in the UM / datasheet, most probably in the Flash section as well.

[Andy_G]

Thank you for your reply Frank.

I've not found anything in either the UM of the Datasheet that applies. 

I appreciate that the processor may have to stall due to flash access times, but there is no mention of this.

If there is a stability risk (temperature dependent or not), then there really should be a warning. Hopefully someone from NXP may be able to offer more information.

[frank_m]

I am not very familiar with the LPC84x types (which are basically M0).

Here the respective section for a M4:

To be honest, I get confused with different documentation strategies of manufacturers.
Others use to separate such features and parameters in a "Datasheet" document, and functional descriptions in a "reference manual" document.
NXP used to put it all in one "User Manual".

I would check the clock settings section (of your UM), perhaps it references flash timing.