Hello Eugene,
Check my answers bellow:
if Core0 execute code from Flash memory, Core1 should run from SRAM. Code can't be fetched from Flash to both MCU at the same time ?
Correct, to get good performance, the slave core image is allocated in an independent bank of SRAM and the master core one in Flash this avoid the bottleneck for the single access to flash but also if you want to place both codes in flash can be done but with a lower performance
Core0 load code of Core1 to SRAM from Flash for execution at any time.
The master core loads the slave image from flash to SRAM after initialization.
Core0 can stop Core1, load new code and restart it again without problems.
Yes, as long as the regions are not overlapped
LPC55S69 has 4 banks of SRAM and any one can be used for Core1 code execution but that bank can't be used by Core0 for any type of accesses, in other case it will be fault.
They could, but ideally they shouldn't be accesing the same bank in order to avoid faults and you should make sure both cores are using different address ranges.
Core0 and Core1 communicate via shared SRAM memory on other bank where Core1 is executed and some mutex is need for avoid simultaneous accesses.
Yes, the LPC55xx/LPC55Sxx provides a simple hardware means called Inter-CPU Mailbox mechanism for communication, this is pretty similar to a mutex for RTOS. There's an example of this in the SDK.
It is no clear how Core1 can wakeup Core0 if it in PowerDown mode. What interrupt , event can be used ?
See Chapter 3 - Example from AN12335 and multicore examples from SDK
While Core0 erase/write Flash memory, it is no access to it from any Core. Core0 should run from SRAM some wait loop. ISR need to be in SRAM if they should be served.
I will suggest to use the Inter-CPU mailbox for this, declare a flag that enable each time one of the cores will modify the flash, this should also be done with the peripherals (UART, SPI, I2C, etc).
Let me know if this helps you
Best Regards,
Alexis Andalon
