LPC55S69 : disable JTAG and SWD

[EugeneHiihtaja]

Hello !

Do I undestand right and SWD/JTAG ports are automatically disabled when Secure boot bit is activated ?

Regards,

Eugene

[jeremyzhou]

Hi Eugene Hiihtaja,

Thank you for your interest in NXP Semiconductor products and for the opportunity to serve you.
1） Do I understand right and SWD/JTAG ports are automatically disabled when Secure boot bit is activated?
-- No, I'm afraid not, and to provide the fastest possible support, I'd like to suggest you learn the detailed information about the secured JTAG via the link.
https://www.digi.com/resources/documentation/digidocs/90001546/concept/trustfence/c_secure_jtag.htm

Have a great day,
TIC

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[EugeneHiihtaja]

Hi !

But how it is applicable for LPC ?

If secure boot is not enabled, SWD debug works some how and may be enabled somewhere in ROM or where.

If I need to disable it I should follow UM Table 142. Debug Features Duplicate register (DEBUG_FEATURES_DP, offset = 0xFA8)

and disable debugging of CPU0, CPU1 and SWDs.

Or what exactly disabled if secure boot is enabled and what I should disable by myself for be secure ?

Thank you !

Regards !

Eugene

[jeremyzhou]

Hi Eugene Hiihtaja，

Thanks for your reply.
1） But how it is applicable for LPC?
-- Yes, and learn more information about it by reviewing 51.7 Debug authentication in the reference manual.

Have a great day,
TIC

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