LPC55S69 and SPI

[jean-marcrouxel]

Hello,

I'm working on a LPC55S69 and I use it as a slave-SPI (connected by a back panel with a board with master-SPI). Because of noise on the SPI, I sometimes have checksum errors on the exchanged frames between both. I wonder if I can use glitch filter on the SPI-bus ? 

I use the following pins for the slave-SPI :

SCK on PIO 0_6

MOSI on PIO 0_3

MISO on PIO 0_2

SSEL0 on PIO 0_4

Regards,

Jean-Marc

[PabloAvalos]

Hi @jean-marcrouxel 

Many thanks for your reply.

Yes, certainly the pins whose type is Type I are only capable to have the glitch filter enabled, so the glitch filter that you are trying to setup for those pins (PIO0_2, PIO0_3, PIO0_4 and PIO0_6) is not possible.

Please let me know if you have more questions.

Sincerely,

Pablo Avalos.

[jean-marcrouxel]

Hi Pablo,

thank you for your reply. Did you do the test one time ? 

I saw these pages too but for me, this SPI configuration is just possible for some IO but not all.

When you see the page 338, we can see that the pins whose type is "I" (PIO0_13 et PIO0_14) can only be configured with glitch filter and these are not the pins I'm using for the SPI. Did you understand the same thing ?

Regards,

[PabloAvalos]

Hi @jean-marcrouxel 

Hoping you are doing well.

The answer to your question is yes, you can use the glitch filter on the SPI-bus by enabling the corresponding bits in the IOCON register.

Please take in consideration that SPI glitch filter is only a 50ns glitch filter.

You can refer to the pages 685-686 on the user manual for this part number: User Manual LPC55S69

I hope this is what you are looking for, please let me know If you have more questions.

Sincerely,

Pablo Avalos.