LPC55S69 : GINT0 and GINT1

[EugeneHiihtaja]

Hello !

Do I understand right and any GPIO pin from group 0 or 1 can be included to GINT0 or 1.

So the same pin can't be in both GINTx but it port 0 pins can be part of GINT1 and vise versa.

Is this so.

But if I select edge sensitivity of all pins what are part of GINT0 group, can I select falling edge or rising edge

for each pin individually or for all of them ?

Regards,

Eugene

[Alice_Yang]

Hello Eugene Hiihtaja,

" any GPIO pin from group 0 or 1 can be included to GINT0 or 1."

-> Yes, any pins from PORT0 and PORT1 can be included to GINT0 and 1. 

" the same pin can't be in both GINTx but it port 0 pins can be part of GINT1 and vise versa."

-> I think the same pin can be in both GINT0 and 1.

"

 can I select falling edge or rising edge

for each pin individually or for all of them 

"

-> Yes, you can config them individually. The PORT_POL register can config each pin polarity:

Have a great day,
TIC

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[EugeneHiihtaja]

Hello Alice !

It means I should include pin to both group if I would like to detect both edges.

Is this so ?

Regards,

Eugene

[Alice_Yang]

YES.

[EugeneHiihtaja]

Hi Alice !

For some reason it dosn't work like this. Please look y request : LPC55S69 : GINTx, detect both edges 

If one pin is included to both GINTx it works, but if more, only falling edge starts to work.

May be special powermanagement API should be called ?

But for me it is blocker.

I need to find out reason and see if ISP,SW2,SW3 on EVK can be programmed in way that all edges are detected for 3 pins at list.

Can https://community.nxp.com/thread/517579  be prioritized some how ?

Regards,

Eugene

[Alice_Yang]

Hello Eugene,

There will other people help you on that thread.