Hello Eugene Hiihtaja ,
For LPC55S66 there is only one flash bank, so we can not running two or more cores main code on one storage bank, because if both core need catch data or command, flash can not response both core request, the core will be stopped and generate fault. Core1's app code storaged in Flash, once power-up, core0 will be startup first, then copied the core1 image into SRAM area and run core1.
Have a great day,
TIC
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