LPC550x Flexcomm maximum frequency clarification

[Bacterius]

Hi,

I am using an LPC550x device. In the user manual it says this:

The FRG maximum allowed output frequency depends on the functionality activated in the
Flexcomm:
For USART, the FRG output frequency Must not be higher than 25 MHz.
For LSPI, the FRG output frequency Must not be higher than 33 MHz.
For I2S, the FRG output frequency Must not be higher than 25 MHz.
For I2C, the FRG output frequency Must not be higher than 20 MHz.
For High Speed SPI, the FRG output frequency Must not be higher than 48 MHz.

This is a problem for me because I use PLL0 to generate a precise MCLK for an audio output, and since the Flexcomms also want to use PLL0, this means I have very little control over the Flexcomm clocks (I am forced to share the fro_hf_div clock with most Flexcomms). Using the FRG to meet the limits above is not ideal because it does not generally produce a 50% duty cycle clock.

Is it allowed to use a higher frequency in FRG output for Flexcomms as long as I divide the clock enough inside the peripheral itself? For example, can I use FCLK[0] = 96MHz and set SPI0.DIV = 8 to bring it into the allowed range?

In my case I have main_clk = 96MHz and I want to use Flexcomm0 at 30MHz and Flexcomm8 at 48MHz and unless I can do the above I do not see how I can achieve this configuration.

Thank you!

EDIT: I am also unclear about all this because UM11424 contradicts itself in at least three locations (the quote above, the remark in 32.4, and the note in the diagram in Figure 95, all of which give different maximum frequencies for FCLK)

[xiangjun_rong]

Hi,

Pls download the data sheet of LPC550x family from the link:

https://www.nxp.com.cn/docs/en/data-sheet/LPC55S0x_LPC550x_DS.pdf

You can check the maximum bit rate clock frequency from it.

This is what I get from Data sheet:

usart in asynchronous mode:

USART master and slave asynchronous mode is 6.25 Mbit/s

I2s module:

The Flexcomm Interface function clock frequency should not be above 48 MHz.

I2C:

SCL clock frequency can be 100KHz in standard mode, 400KHz in fast mode, 1MHz in fast mode plus.

SPI:

the maximum supported bit rate
for SPI slave receive mode is 50 Mbit/s and for slave transmit mode is 25 Mbits/s

the maximum supported bit rate
for SPI master mode (transmit/receive) is 50 Mbit/s.

Hope it can help you

BR

XiangJun Rong

[Bacterius]

Hi XiangJun, thank you for your reply.

I understand the bit rate limitations, my question is more about the Flexcomm peripheral clock itself (FCLK). For example can I use a 48MHz clock to USART master and divide it down to < 6.25 Mbaud? Or is the peripheral input clock limited to 25MHz as described in the user manual...

[xiangjun_rong · Accepted solution]

Hi,

As the following figure, the main_clk can  reach up to 150MHz, the FRG can be a divider by 2 at most, the FCLK can be 75Mhz at least.

So I think the FCLK frequency is not limited by the FRG module, it is only limited by the FlexComm target  module.

Hope it can help you

BR

XiangJun Rong