LPC546xx: SCTimer/PWM clocking

[giusloq]

I can't understand the clocking system of SCTimer/PWM module in LPC546XX MCUs.

CLKMODE=0x0 selects system clock for SCTimer counter clocking. Is this clock divided by SCTCLKDIV or not?

For example, if I have a system clock of 220MHz (on LPC54628) and SCTCLKDIV=1 (divide by 2), what is the SCTimer counting clock frequency? 220MHz or 110MHz? It seems to me it is always 220MHz, so it doesn't depend on SCTCLKDIV.

It is strange, because CLOCK_GetSctClkFreq() returns 110MHz, but I think its 220MHz.

When SCTCLKDIV is used? Only if I use CLKMODE=0x2 or 0x3 and CLKSEL=0xE or 0xF (Input 7 as the clock)?

I also read another note:

Remark: The maximum frequency for the SCTimer/PWM clock is 100 MHz.

If I have a system clock of 220MHz, couldn't I use CLKMODE=0x0 (counter clocked by system clock, apparently without divider)?

[xiangjun_rong]

Hi,

I agree with you, if you set up CLKMODE=0x0 , the system clock is selected as tick for the SCTimer counter, the system clock is the CPU clock as the following fig rather than SCT_IN7 clock. So if you select the CLKMODE=0x0, you can NOT change the SCT clock with changing the SCTCLKDIV value.

There is a remark that the SCT clock maximum frequency is 100MHz, pls refer to 16.3 Basic configuration in UM10912.pdf

Hope it can help you

BR

XiangJun Rong

[giusloq]

So if you select the CLKMODE=0x0, you can NOT change the SCT clock with changing the SCTCLKDIV value.

Ok, so SCT will be clocked with 220MHz (in my case).

There is a remark that the SCT clock maximum frequency is 100MHz, pls refer to 16.3 Basic configuration in UM10912.pdf

Yes, this is exactly the note I read. What I don't understand and it isn't clear, does this limitation of 100MHz valid with CLKMODE=0x0 (system clock)? I suspect this limitation is valid only for clocks coming from the inputs (CLKMODE=0x2/0x3), but not for system clock (CLKMODE=0x0).

Otherwise, with a system clock of 220MHz (or 180MHz or 120MHz), I wouldn't be able to use CLKMODE=0x0.

Could you confirm?

[xiangjun_rong]

Hi,

The limitation of 100Mhz clock frequency is for the SCT itself, in other words, if you use the system clock as tick, you have to reduce the system clock to 100MHz, even if the cpu can reach up to 220MHz.

If you do want to run the cpu in 220MHz, I suggest you use the SCT_IN7 as tick input clock for SCT.

Hope it can help you

BR

XiangJun Rong

[giusloq]

Are you sure? I'm sorry, but I have some doubts yet for two reasons.

The first: there are many SDK examples for LPC54628 EVB that configure SCTimer to use system clock (CLKMODE=0x0), that is configured at 220MHz. Considering the limitation of 100MHz, these examples are all wrong, but they works on the board.

The second: I found another thread on this forum with a similar argument. The answer from another NXP guy (ZhangJennie) is different from yours:

There are two type of input for SCT, the the 100MHz clock limitation is only valid for the clock source inputted from external pads (SCT_IN7), if you use system clock as the SCTimer/PWM clock source, the system clock frequency can be greater than 100MHz.

[xiangjun_rong]

Hi,

I have checked the code sctimer_pwm_with_duty_cycle_change, as you have said, it uses 220mhz system clock to generate 24Khz PWM signals, it appears that the example works fine.

I will confirm  with Jennie if the system clock can reach up to 220MHz when the system clock functions as a tick.

BR

XiangJun Rong

[xiangjun_rong]

HI,

I confirmed with Jennie, the 100MHz clock restriction is only for SCT_IN7 clock input source or the  external pin input clock source of SCT module, if the SCT uses system clock as tick, it can reach up to 220mhz.

Sorry.

BR

XiangJun Rong