The SPI timing spec is defined in data sheet of LPC5460x.pdf, which can be downloaded from the link.
If the SPI is configured as master, we have a delay register to define the delay timing. For detailed inf, pls refer to Table 453. SPI Delay register (DLY, offset 0x404) bit description in UM10912.pdf.
I copy part of it here from data sheet:
Hope it can help you
Thank you for the quick response dear XiangJun Rong.
We are configuring the MCU as an SPI slave (1.71 V ≤ Vdd ≤ 2.7V, CCLK ≤ 100 MHz (FLEXCOMM clock has to be less than 48 MHz from what I understand from the user manual)). I am specifically looking for timings related to the select line (SSEL). Please see the diagram below. If you can share the numbers, that will be extremely helpful for us.
Regarding the minimum time between the falling edge of the SSEL signal and the first edge of SCK in CPHA=0, I think the time must meet the tDS(Data set-up time) spec in SPI slave mode. For the minimum high pulse time of the SSEL signal, it is not defined in data sheet.
Thank you for the clarification. Any chance to get the value for "minimum high pulse time of the SSEL signal"? We are connecting our LPC54606 to a device (master) that stream data continuously and so we need to make sure the frame select pulse is long enough that we are within the spec and short enough that we do not lose any data bits.
NOTE: The device doesn't conform to the standard SPI protocol for the SSEL (so we cannot use the device's SSEL) and so we have to generate our own SSEL using an FPGA