LPC54605 Flexcomm clock question

[guitardenver]

On the LPC54605J256 part, I am running the main clock at 180MHz. I'm configuring the SPI and I had a question about the clock configuration.

The datasheet says "Flexcomm Interface function clock frequency should not be above 48MHz". Since my main clock is 180MHz, I want to use the FRG for the common Flexcomm clock so I can use the FRGCTRL to divide the 180MHz down to the 30MHz clock I want.

But, if I want to use a UART on another peripheral, the datasheet says the FRGDIV value must stay at 255. I can not achieve a clock of 30MHz with the FRGCTRL.

Flexcom Clock (30MHz) = 180MHz / (1 + MUL/256)

MUL would have to be 1280. Which can not fit in the MUL register.

My question is:

1) Can the input to a specific flexcomm (flexcomm0) be 180Mhz, then use the SPI0 DIV register to divide by 6 to get my 30MHz. Or does the clock before the SPI DIV have to be less than 48MHz to begin with?

My code is working with the frg_clk clock being 180Mhz and using the SPI DIV to bring it down to 30Mhz. But I want to make sure this is a valid operational mode.

End goal, I need the following to work:
Main clock = 180MHz

SPI0 (flexcomm0) = 30MHz

Flexcomm2 (UART) = 600Buad to 115200Baud

[jaroslaw_gorski]

Can the Flexcomm interfaces use any of the crystal oscillator derived clocks for interface clock if main clock and pll clock frequency is over 48MHz and Audio PLL is not available? Are the FRO oscillators the only option then? 

[jeremyzhou · Accepted solution]

Hi Matt Lang,

Thank you for your interest in NXP Semiconductor products and
for the opportunity to serve you.
Q1)Can the input to a specific flexcomm (flexcomm0) be 180Mhz, then use the SPI0 DIV register to divide by 6 to get my 30MHz. Or does the clock before the SPI DIV have to be less than 48MHz to begin with?
-- The flexcomm interface's clock shouldn't be above the 48 MHz means that the clock before the SPI DIV has to be less than 48MHz to begin.
Hope this is clear.

Have a great day,
TIC

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