LPC54018 SPI

[Sukumar_M]

if I set transfer delay 3,4,5,9,10 the clock pulse are 16 pulses why?

and I set transfer delay 1,2,6,7,8 the first pulse width should be High.93de70ab-bfba-476b-9bfb-0bde32be783e.jpg6861a5ee-5d24-4982-bc35-b1cd0560bc06.jpg

[Sukumar_M]

Thanks for Support to me.

[xiangjun_rong]

Hi,

If you want to validate the FRAME_DELAY time, you have to set the EOF bit in FIFOWR register for each transfer.

Hope it can help you

BR

XiangJun Rong

xiangjun_rong_0-1648192711087.png