LPC4370 DMA Issues

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LPC4370 DMA Issues

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rulamp
Contributor III

SDK: LPC Open v3.02
IDE: MCUXpresso v11.21
Hardware: Link2 (one as a programmer/debugger, the other as the target)

Update:
I overlooked needing to add the entries in the GPDMA_LUTPerBurst and GPDMA_LUTPerWid arrays. Once I added the values for the ADCHS, the Peripheral to Memory DMA seems to fire and copies the data properly, but only does it a handful of times before the program freezes. I have a breakpoint set in the DMA_IRQHandler, however, the program execution never gets there.

Any idea what I am overlooking in order to have continuous transfers occur? From my understanding, the FIFO_FULL flag will be set when the FIFO is equal to or above the level set and this should trigger a DMA transfer. When the transfer occurs, this should clear the ADCHS FIFO and the everything should repeat. Please let me know if I am wrong here.

Please see attached for my code. Thanks.
ORIGINAL:
Hello. I Have been struggling with this for quite some time. 

The goal is to use DMA to transfer data from the ADCHS FIFO to user memory.
I have not been able to get his to work.

To simplify things, I first set up a memory to memory transfer with the DMA controller as the flow controller. This works correctly.

Next I tried a memory to memory transfer with DMA  controller as flow controller, but the source address is the address of a peripheral register.
Registers I have tried:
0x400F001C (ADCHS->CONFIG)
0x400F0200 (ADCHS->FIFO_OUTPUT)
0x40002030 (GPDMA->CONFIG)

I noticed that the needed DMAMUX values for channels 7 and 8 (ADCHS Read/Write) are not included in the SDK. I added them as well as the entries in *GPDMA_LUTPerAddr.

Is there an example of using DMA with the High Speed ADC on the LPC4370?
Why isn't the manual transfer working?

Thanks


 

 

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rulamp
Contributor III

The solution I came to was that these three registers need to be re-initialized in order for another transfer to occur.

LPC_GPDMA->CH[dmaCh].SRCADDR
LPC_GPDMA->CH[dmaCh].DESTADDR
LPC_GPDMA->CH[dmaCh].CONFIG |= 1

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rulamp
Contributor III

The solution I came to was that these three registers need to be re-initialized in order for another transfer to occur.

LPC_GPDMA->CH[dmaCh].SRCADDR
LPC_GPDMA->CH[dmaCh].DESTADDR
LPC_GPDMA->CH[dmaCh].CONFIG |= 1
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xiangjun_rong
NXP TechSupport
NXP TechSupport

Hi,

The ADC code in LPCOpen package is based on software triggering, this is the example code ADC triggering mechanism:

The CTimer generates interrupt with a fixed period, in the ISR of CTimer, software trigger is used to trigger ADC. When the ADC has finished conversion, the ADC interrupt is generated to read the ADC sample.

Because the example uses interrupt mode, it is not possible to get very high ADC conversion rate.

Hope it can help you

BR

XiangJun Rong

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rulamp
Contributor III

Yes I understand all of that already. And I understand that the examples are software triggered. I do not have a problem with the ADC. I have a problem with DMA.

I cannot get the GPDMA peripheral to work properly. I need help with the DMA.

Thanks!

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xiangjun_rong
NXP TechSupport
NXP TechSupport

Hi,

I attach a C file, but it is not fully tested, pls have a try.

BR

XiangJun Rong

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rulamp
Contributor III

Thank you for your help.

Update:
I discovered that the DMA channel is disabled after a transfer is completed and must be re-initialized in order for another DMA transfer to occur. This is crazy to me. I need to run the HSADC at 80MS/s and must use DMA to move data. If I have to re-initialize the DMA channel after every transfer, that is a lot of overhead.

Questions:
1) Is there any way to keep the DMA channel enabled so that transfers will occur automatically every time the HSADC->STATSU0->FIFO_LEVEL_TRIG flag is set?
2) Any example code or advice for how to use the HSADC at 80MS/S and use DMA to transfer data with minimal overhead?

Thanks,


Original post:
I slightly modified the program to do three things.
1) Used memalign the sample destination memory
2) Added lines to print to console (DEBUGOUT) the values of sample[0] to sample[20].
3) I removed the line that disables the DMA in the handler and use the SDK function Chip_GPDMA_Interrupt to read and clear the flags.

The problem is that the ADC runs properly and continuously, but the DMA transfer only occurs once. From my understanding, the DMA transfer should occur every time the FIFO reaches the level set to trigger the FIFO_FULL flag interrupt.

I have two specific questions:
1) Any ideas why the DMA transactions don't occur repeatedly when the FIFO reaches the level set?
2) In the DMA Channel Control Register (LPC_GPDMA->CH[DMA_CH].CONTROL address 0x4000 210C) the TRANSFERSIZE value will be ignored as the peripheral is the flow controller, correct?

Thanks again!

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