LPC4337 RESET

[mazejun]

The P2_7 pin of the LPC4337 microcontroller lacks an external pull-up resistor. Upon initial power-up, this pin is detected in a high state, thereby selecting the boot source as the internal flash memory.

Subsequently, the pin is multiplexed and configured as part of the External Memory Controller (EMC) interface within the application software. The software also initializes a windowed watchdog timer. In the event of a software fault that triggers a watchdog reset, a critical question arises regarding the boot process:

Does the LPC4337 re-sample the state of the P2_7 pin after such a watchdog reset?

This is pertinent because the EMC configuration routine typically drives the P2_7 pin to a low logic level. If the pin state is re-evaluated post-reset, the low level could potentially cause the device to enter a boot mode different from the initial internal flash boot, leading to an unexpected system state.

Could NXP's technical support or applications engineering team clarify the boot pin sampling behavior following a watchdog reset in this specific scenario? A definitive explanation would be greatly appreciated.

[Harry_Zhang]

HI @mazejun 

Based on the LPC4337 user manual and the reset hierarchy in UM10503, a WWDT  reset is a full‑chip reset. After such a reset, the Boot ROM runs again and re‑samples all boot configuration pins, including P2_7.

Since P2_7 has no external pull‑up and may be driven low earlier by the EMC configuration in the application, the pin level at reset may be low. This can cause the device to select a different boot mode after a watchdog reset compared to the initial power‑up.

BR

Harry

[wegan456]

By selecting the boot source as the internal flash memory, the LPC4337 starts execution from internal flash. Subsequently, the P2_7 pin is multiplexed and configured as part of the External Memory Controller (EMC) interface within the application software. The software also initializes a windowed watchdog timer.    ExperianCredit