LPC4330 User Manual / LPCOpen bugs

[lpcware]

Content originally posted in LPCWare by pierre on Sat Sep 20 07:02:31 MST 2014
Hello !

I found a few bugs in the LPC4330 manual (last revision) :

1) User manual "bug"

12.6.3.2 PLL0USB control register
12.6.4.2 PLL0AUDIO control register

Register description says : Bit 1 BYPASS : Value 1 : PLL0 input clock sent to post-dividers (default).

12.7.4.2 PLL0 description, Figure 33

Figure means : BYPASS really bypasses everything, PLL0 input clock is sent to the output, and post-divider is ignored.

After testing, the figure is right, and the register description is wrong.

2) LPCOpen bug

uart_18xx_43xx.c uses the wrong branch clocks to calculate baud rates, Chip_UART_GetClockIndex().
It should be CLK_APBx_UARTx, not CLK_MX_UART1.

CLK_APBx_UARTx is the clock which controls the hardware baud rate generator.
CLK_MX_UART1 simply controls the cpu bus interface.

I change the CPU frequency on the fly. This works very well.
Then I set CLK_APB0_UART0 to something else than CLK_MAINPLL, since I don't want to recompute the baud rates every time : it did not work.

Fix in uart_18xx_43xx.c :

STATIC CHIP_CCU_CLK_T Chip_UART_GetClockIndex(LPC_USART_T *pUART)
{
CHIP_CCU_CLK_T clkUART;

if (pUART == LPC_USART3) {
clkUART = CLK_APB2_UART3; // CLK_MX_UART3;
}
else if (pUART == LPC_USART2) {
clkUART = CLK_APB2_UART2; // CLK_MX_UART2;
}
else if (pUART == LPC_UART1) {
clkUART = CLK_APB0_UART1; // CLK_MX_UART1;
}
else {
clkUART = CLK_APB0_UART0; // CLK_MX_UART0;
}

return clkUART;
}

After starting crystal, add UART init code :

Chip_UART_TXDisable(DEBUG_UART);
Chip_Clock_SetBaseClock(CLK_BASE_UART0, CLKIN_CRYSTAL, true, false );
Chip_Clock_EnableOpts(CLK_APB0_UART0, true, true, 1);
Chip_UART_SetBaudFDR(DEBUG_UART, 115200);
Chip_UART_TXEnable(DEBUG_UART);

It works now.

[lpcware]

Content originally posted in LPCWare by xianghuiwang on Mon Sep 22 18:54:33 MST 2014
Thanks, we will confirm and correct these issues.