CLK sdram and i2s0

[lpcware]

Content originally posted in LPCWare by gvandenbosch on Tue Jan 05 19:18:06 MST 2016
Hello,

My hardware designer connected the SDRAM clock to CLK0 and I2S0 to CLK2.

Only I am having problems now getting this to work in code, I had the following code at first to set the CLK:

/* Select EMC clock-out */
LPC_SCU->SFSCLK_0 = (MD_PLN | MD_EZI | MD_ZI | MD_EHS);
LPC_SCU->SFSCLK_1 = (MD_PLN | MD_EZI | MD_ZI | MD_EHS);
LPC_SCU->SFSCLK_2 = (MD_PLN | MD_EZI | MD_ZI | MD_EHS);
LPC_SCU->SFSCLK_3 = (MD_PLN | MD_EZI | MD_ZI | MD_EHS);

If I remove any of those lines the SDRAM stops working, but it is only connected to CLK0.
Then I found: http://www.nxp.com/documents/application_note/AN11508.pdf

It says that all 4 need to be configured or you can combine CLK0 and CLK2.

But my I2S0 clock is hard wired to CLK2, which now is used by the EMC already.
Is there any way to make this work in software?

Cheers,
Gerard

[lpcware]

Content originally posted in LPCWare by wmues on Wed Jan 06 02:24:38 MST 2016
You can not make this work in software.
Your hardware designer has to fix it in hardware.