M4MEMMAP Register

[lpcware]

Content originally posted in LPCWare by MikeSimmonds on Sun Nov 16 05:17:21 MST 2014
I have been using the 1778 for a couple of years now, and I think I understand the clocks, emc and peripherals well enough.

I have now taken an interrest in the LPC-Link2 board [4370] and I am overwhelmed by the increased complexity of the
clocking and peripheral clocking and 'reset generation unit'. How ever, I feel that with some study time with the UM,
I can master these. And it is reassuring to find the e.g. the UARTs and the RTC are very similar (if not identical).

The boot process is also a lot more complicated (in the details) but I think I have 'got my head round' this too.

Where I am most confused is with the concept of memory mapping.
[Note: for now I am only interrested in single core -- M4 -- examples, and because I have the LPC-Link2 board,
booting either from memory via the DFU-Util and booting from SPI Flash (I'll worry about actually programming
the SPI Flash later.)]

It seems to me from my reading so far, that I can 'link my code' to address zero and use the same image both
from DFU download and from SPI flash depending on JP1 boot pin select. And I think that the rom boot code
will set the M4MEMMAP correctly for me.

Can anyone confirm my hypothesis. Are there and pitfalls to avoid?
Are there any special considerations for debugging one as opposed to the other?

Thanks for listening, Mike.

[lpcware]

Content originally posted in LPCWare by MikeSimmonds on Mon Nov 17 08:49:59 MST 2014
When changing MxMEMMAP in running code [e.g. after copying from some NVR storage to internal static ram]
are there any dsb/dmb/isb requirements?

Cheers, Mike

[lpcware]

Content originally posted in LPCWare by MikeSimmonds on Mon Nov 17 08:19:07 MST 2014
Thankyou for the link.

However, it would help (me, at least) if the existance of this document were more obvious.
Suggestion, in the next release of the user manual(s) add a reference to the Tech Note.

Also, I came across a theory in another post that I can't find again that the MxMEMMAP registers
work as if the address and the remeap are XORED rather than ADDED.

Can you confirm/deny/otherwise clarify this assertion.

Regards, Mike

[lpcware]

Content originally posted in LPCWare by bavarian on Mon Nov 17 07:08:51 MST 2014
Hello Mike,

have you seen this?

http://www.nxp.com/documents/technical_note/TN00006.pdf

In principle you're right. The bootcode will set the register correctly for, you could write a binary mapped to 0 which runs from different memory areas in case the M4MEMMPAP is written correctly.

Regards,
NXP Support Team.