LPC_SC->PCLKSEL0 |= 1<<1; //100 MHz
LPC_SC->PCLKSEL0 |= 1<<1; //96 MHz
Your code is setting the clock division for the watch dog timer. The timer0 position is at bits 3-2 (div << 2).
The default for timer 0 is CCLK/4 so you need to write "01" to bits 3-2 (0x01 << 2) for 100MHz. So the two
lines above don't make any sense.
The math is easy.
1.You set the clock to the timer with PCLKSEL0.
2. Start the timer and it will count up to your match value and interrupt.
3. The timer resets and counts up again.
For 10msec interrupt:
Timer 0 clock = 100MHz clock that would be 100nsec per count.
Desired count timer is 10msec = .01sec,
Every Timer0 count will equal 100nsec.
Number of counts per interrupt = .01 sec / 100nsec per count = 1000000 counts. MR0 = 1000000.