LPC1549 SCTimer bug report

[waterdragon900]

Being a bit new to all this, apologies if I have posted in the wrong place. (I confess that I don't really understand or like these modern forums with 'likes' and 'follows' and other such nonsense.)

I wanted to report an apparent bug in the LPC1549 device but it seems that there is no bug-tracker site active any more.

Anyway, here's the bug which manifests when using any SCTimer in non-unified mode whereby the timer runs as two 16-bit independent timers - high and low.

Each split timer has a separate HALT bit allocated within the CTRL register - HALT_H and HALT_L.

The apparent bug is that setting the HALT_L bit not only stops the lower timer but also stops the higher timer. Big show-stopper if you don't know about it.

[waterdragon900 · Accepted solution]

Looks like I missed a "Remark" in the user manual that states:

"If the SCTimer/PWM is operating as two 16-bit counters, events can only modify  
the state of the outputs when neither counter is halted. This is true regardless of what  
triggered the event."

Since I was depending on output changes to monitor the functioning of the timers, it appeared as a bug to me.

So much for the upper and lower timers being independent as claimed! It's simply not true.

I think this should have been made as a prominent warning in the manual instead of just one of thousands of "remarks" that I frankly don't have the time or patience to read through.

Anyway, apologies to anyone whose time I have wasted with this post.

[jeremyzhou]

Hi Colin Burn,

Thank you for your interest in NXP Semiconductor products and the opportunity to serve you.

Thanks for your reporting, and I'll check it later.
Have a great day,
TIC

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